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october 2003 1/88 ade3000 ade3050 ade3100 ade3200 ade3250 ade3300 lcd display engines with integrated dvi, adc and yuv ports ? the ade3xxx is a family of highly integrated display engine ics, enabling the most advanced, flexible, and cost-effective system-on-chip solutions for lcd display applications. the ade3xxx line-up covers the full range of applications from xga analog only to dual sxga smart panel designs. all twelve ade3xxx devices are pin-to-pin compatible and use a common software platform. feature overview n programmable context sensitive? scaling n high-quality up-scaling and down-scaling n dual input: dvi / vga n integrated 9-bit adc/pll n integrated dvi-rx n iqsync? autosetup n integrated programmable timing controller n integrated pattern generator n perfect picture? technology n srgb 3d color warp n integrated osd n advanced emi reduction features n framelock operation with safety mode? n serial i2c interface n low power 0.18 m process technology product selector 208-pin pqfp package product input interface support output format support analog dvi yuv resolution tcon ade3000 xx up to xga 75hz ade3000t xx up to xga 75hz x ADE3000SX xx up to sxga 75hz ADE3000SXt xx up to sxga 75hz x ade3050 xx up to xga 75hz ade3050t xx up to xga 75hz x ade3050sx xx up to sxga 75hz ade3050sxt xx up to sxga 75hz x ade3100 xxx up to xga 75hz ade3200 xxx up to xga 75hz x ade3250 xxx up to sxga 75hz x ade3300 xxx up to sxga 75hz
ade3xxx 2/88 third generation context sensitive? scaler l sharper text with edge enhancement l ram based coefficients for unique customization l 5:1 upscale and 2:1 downscale l independent x - y axis zoom and shrink l bob de-interlacing eliminates jaggies and motion artifacts analog rgb input l 140mhz 9-bit adc l ultra low jitter digital linelock pll l composite sync and sync on green support secure dvi? receiver l single link dvi receiver l input pixel rate from 25 to140 mhz l low power mode with activity detection l compatibility with all dvi compliant transmitters digital tv video input l vesa vip 1.1, 2.0 and ccir656 compliant l 25 to 75 mhz input clock iqsync? autosetup l autosetup configures phase, clock, level, and position l supports continuous calibration for reduced user intervention l detects activity on all inputs and selects the active source l compatible with all standard vesa and gtf modes perfect picture? technology l video & picture highlight zoning l supports up to 7 different windows l independent window controls for contrast brightness, sharpness, and color perfect color? technology l programmable 3d color warp l digital brightness, contra st, hue, and saturation gamma controls for all inputs l simple white point control l compatible with srgb standard l true color dithering for 12- and 18-bit panels l temporal and spatial dithering l 30-bit programmable gamma table osd engine l 256 ram based 12x18 characters l 1 and 4-bit per pixel color characters l bordering, shadowing, transparency, fade-in, and fade-out l supports font rotation l up to 4 sub windows l 32 entry truecolor lut programmable timing controller (tcon) l highly-programmable support for xga, ttl and rsds smartpanels l dual function ttl and rsds outputs l advanced flicker detection and reduction l 12 programmable timing signals for row/ column control l wide range of drivers & tcon compatibility l simulation tools for easy programming l supports complex polarity generation for ips panels advanced emi reduction features l flexible data inversion / transition minimization, single, dual, and separate l per pin delay, 0 to 6ns in 0.4ns increments l adaptive slew rate control outputs l supports 18/24/36/48-bit rsds outputs l differential clock l spread spectrum -programmable digital fm modulation of the output clock with no external components output format l supports resolutions up to sxga @ 75hz l supports 6 or 8-bit panels l support double or single pixel wide formats
3/88 ade3xxx table of contents chapter 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.1 pin description ........................................................................................................... ......... 6 chapter 2 ade3xxx functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.1 global control block .. ........................................................................................................ 13 2.2 fm frequency synthesizer ................................................................................................ 17 2.3 adc block .................................................................................................................. ........ 18 2.4 line lock pll block ........................................................................................................ ... 19 2.5 digital video input (dvi) .................................................................................................. ... 22 2.6 hdcp block ................................................................................................................. ...... 27 2.7 yuv block .................................................................................................................. ........ 29 2.8 sync retiming block ........................................................................................................ .. 30 2.9 sync measurement block .................................................................................................. 32 2.10 sync mux block ............................................................................................................ ...... 40 2.11 data mux block ............................................................................................................ ...... 42 2.12 data measurement block ................................................................................................... 4 2 2.12.1 edge intensity .......................................................................................................... ..........................43 2.12.2 pixel sum ............................................................................................................... ............................43 2.12.3 min / max ............................................................................................................... ............................43 2.12.4 pcd ..................................................................................................................... ..............................43 2.12.5 h position min / max .................................................................................................... ......................43 2.12.6 v position min / max .................................................................................................... ......................44 2.12.7 de size ................................................................................................................. .............................44 2.13 programmable nonlinearity block ...................................................................................... 48 2.14 scaler block .............................................................................................................. ......... 49 2.15 output sequencer block .................................................................................................... 52 frame synchronization ......................................................................................................... ..............................52 timing unit ................................................................................................................... .......................................52 signal generation ............................................................................................................. ..................................52 2.16 timing controller (tcon) block ...... .................................................................................. 55 2.17 pattern generator block ................................................................................................... .. 60 screen split .................................................................................................................. ......................................60 pattern engine ................................................................................................................ ....................................61 borders ....................................................................................................................... ........................................61
ade3xxx 4/88 2.18 srgb block ................................................................................................................ ........64 2.18.1 parametric gamma correction and digital contrast/brightness control .......................................... 64 2.18.2 color space warp ........................................................................................................ ..................... 64 2.19 osd block ................................................................................................................. .........66 2.20 flicker block ............................................................................................................. ..........72 2.21 gamma block ............................................................................................................... ......74 2.22 apc block ................................................................................................................. .........74 2.23 output mux block .......................................................................................................... .....75 2.24 pulse width modulation (pwm) block ................................................................................77 2.25 dft block ................................................................................................................. ..........79 2.26 i2c ram addresses ...........................................................................................................8 0 chapter 3 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.1 absolute maximum ratings ................................................................................................82 3.2 power consumption matrices .............................................................................................82 3.3 nominal operating conditions ............................................................................................83 3.4 preliminary thermal data ..... ..............................................................................................84 3.5 preliminary dc specifications .. ..........................................................................................84 3.5.1 lvttl 5 volt tolerant inputs with hysteresis ............................................................................. ...... 84 3.5.2 lvttl 5 volt tolerant inputs ............................................................................................. ................ 84 3.5.3 lvttl 5 volt tolerant i/o with hysteresis ................................................................................ ........ 84 3.5.4 lvttl outputs ............................................................................................................ ...................... 84 3.6 preliminary ac specifications . ..........................................................................................85 chapter 4 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 chapter 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
5/88 ade3xxx 1 general description the ade3xxx family of devices is capable of implementing all of the advanced features of today's lcd monitor products. for maximum flexibility, an external microcontroller (mcu) is used for controlling the ade3xxx and other monitor functions. the ade3xxx architecture unburdens the mcu from all data-intensive pixel manipulations, providing an optimal blend of feature and code customization without incurring the cost of a 16-bit processor or memory. the key interactions between the monitor mcu and the ade3xxx can be broken down into the features shown in the table below. figure 1: ade3xxx block diagram table 1: ade3xxx features (sheet 1 of 2) feature description of ade3xxx operation blocks used pages power up / initialize when power is first applied, the ade3xxx is asynchronously reset from a pin. the mcu typically programs the ade3xxx with a number of default values and sets up the ade3xxx to identify activity on any of the input pins. all preconfigured values and rams, such as dvi settings, line-lock pll settings, video input modes (yuv), osd characters, lcd timing values (output sequencer), scale kernels, gamma curves, srgb color warp, apc dithering, output pin configuration (omux), etc. can be preloaded into the ade3xxx. the typical end state is that the ade3xxx is initialized into a low power mode, ready to turn active once the power button is pressed. glbl smeas dvi llk adc yuv osd scaler gamma srgb outseq tcon apc omux 13 32 22 19 18 29 66 49 74 64 52 55 74 75 activity detect when the monitor has been powered on, the inputs can be monitored for active video sources. based on the activity monitors, the mcu chooses an input or power down state. smeas 32 yuv port analog port dvi port scaler with sclk f. s y n th p. g e n output format fm f. s y n t h llkpll dmeas smeas inclk sclk dotclk color management osd gamma lut data ctrl vertical keystone
pin description ade3xxx 6/88 1.1 pin description sync / timing measurement once an input source is selected, all available information on frequencies and line/pixel counts is measured for the selected source and made available to the mcu. smeas 32 mode set once the mcu has determined the matching video mode or calculated a video mode using a gtf algorithm, the datapath is programmed to drive the flat panel. clock frequencies for the internal memory and datapath are also set at this time. glbl llk srt dmux smux scaler pnl 13 19 30 42 40 49 48 autotune when the mcu calls for an autotune, the mcu sets up an iterative loop to search for the best phase, gain, offset, etc. at each step of the loop, the mcu kicks off a test in which the ade3xxx which performs extensive statistical analysis of the incoming data stream. the results of the analysis are made available to the mcu which is responsible for the optimization algorithm. dmeas llk adc smux srt 47 19 18 40 30 digital contrast / brightness in response to user osd control, the mcu can program single 8b registers that set brightness and contrast for each color channel independently. srgb 64 white point control in response to user osd control, the mcu can program three 8b registers that set the white point for the output. srgb 64 gamma adjustment the mcu can program the gamma rams to implement 10b accurate color transformations. gamma 74 srgb control the srgb block allows simple, intuitive color control with just a few registers. srgb 64 pattern generation for production testing, the ade3xxx can be programmed by the mcu to output a wide set of test patterns. pgen 60 flicker reduction for smart panel applications, the mcu can set up the flicker detection block to report any correlation with the polarity inversion signal. the mcu can then change the polarity inversion to a non-correlating pattern to eliminate flicker. flicker tcon 72 55 hdcp the ade3xxx contains the blockcipher and decryption functions - interactions over ddc are managed by the mcu for maximum flexibility. the mcu models the slow (frame rate, e.g. 60 hz) authentication handshaking and state machine whereas the ade3xxx handles the fast (line rate, e.g. 50 khz) decryption state machine. hdcp 27 backlight control the ade3xxx provides two pwm outputs for direct control of the power components in a typical backlight. the mcu sets up the registers and enables the function. pwm 77 low power state to enter a low power state, the mcu can gate of most of the clocks and put the analog blocks into a low power standby state. the dvi block will still report activity in standby, allowing "wake on connection" operation. glbl 13 table 2: pin description (sheet 1 of 7) pin # name type description 1 yuv6 input tv video input port: data 6 2 yuv5 input tv video input port: data 5 3 yuv4 input tv video input port: data 4 4 yuv3 input tv video input port: data 3 5 yuv2 input tv video input port: data 2 table 1: ade3xxx features (sheet 2 of 2) feature description of ade3xxx operation blocks used pages
7/88 ade3xxx pin description 6 yuv1 input tv video input port: data 1 7 yuv0 input tv video input port: data 0 8 yuvclk input tv video input port: clock 9 dvdd18 power digital 1.8v vdd 10 dgnd power digital ground 11 dvdd18 power digital 1.8v vdd 12 dgnd power digital ground 13 agnd power analog ground 14 avdd18 power analog 1.8v vdd 15 avdd33 power analog 3.3v vdd 16 rx2m input dvi receiver channel 2 minus input (red) 17 rx2p input dvi receiver channel 2 plus input (red) 18 agnd power analog ground 19 avdd33 power analog 3.3v vdd 20 rx1m input dvi receiver channel 1 minus input (green) 21 rx1p input dvi receiver channel 1 plus input (green) 22 avdd33 power analog 3.3v vdd 23 rx0m input dvi receiver channel 0 minus input (blue) 24 rx0p input dvi receiver channel 0 plus input (blue) 25 avdd33 power analog 3.3v vdd 26 agnd power analog ground 27 rxcp input dvi receiver clock channel plus input 28 rxcm input dvi receiver clock channel minus input 29 avdd33 power analog 3.3v vdd 30 rext passive 1% 475 ohm resistor to analog 3.3v vdd 31 avdd33 power analog 3.3v vdd 32 avdd33 power analog 3.3v vdd 33 agnd power analog ground 34 agnd power analog ground 35 agnd power analog ground 36 rbias passive 1% 2.0 kohm resistor to analog ground 37 agnd power analog ground 38 avdd18 power analog 1.8v vdd 39 agnd power analog ground 40 avdd33 power analog 3.3v vdd 41 agnd power analog ground 42 avdd18 power analog 1.8v vdd 43 agnd power analog ground 44 avdd18 power analog 1.8v vdd table 2: pin description (sheet 2 of 7) pin # name type description
pin description ade3xxx 8/88 45 agnd power analog ground 46 avdd18 power analog 1.8v vdd 47 xgnd power crystal oscillator ground 48 xtal_in input crystal osc illator input 49 xtal_out output crystal oscillator output 50 xvdd18 power crystal oscillator 1.8v vdd 51 lvdd18 power line lock pll 1.8v vdd 52 lgnd power line lock pll ground 53 csync input composite sync input - for sync on green 54 vsync input vertical sync input 55 hsync input horizontal (or composite) sync input 56 agnd power analog ground 57 agnd power analog ground 58 avdd33 power analog 3.3v vdd 59 avdd33 power analog 3.3v vdd 60 agnd power analog ground 61 avdd18 power analog 1.8v vdd 62 agnd power analog ground 63 refb passive 1% 15.0 kohm resistor to analog ground 64 refmb passive connect to analog ground 65 refpb passive 470nf capacitor to analog ground 66 agnd power analog ground 67 agnd power analog ground 68 inb input analog video port: blue channel input 69 avdd33 power analog 3.3v vdd 70 avdd33 power analog 3.3v vdd 71 refcb passive 100nf capacitor to analog ground 72 agnd power analog ground 73 avdd18 power analog 1.8v vdd 74 avdd18 power analog 1.8v vdd 75 refg passive 1% 15.0 kohm resistor to analog ground 76 refmg passive connect to analog ground 77 refpg passive 470nf capacitor to analog ground 78 agnd power analog ground 79 agnd power analog ground 80 ing input analog video port: green channel input 81 avdd33 power analog 3.3v vdd 82 avdd33 power analog 3.3v vdd 83 refcg passive 100nf capacitor to analog ground table 2: pin description (sheet 3 of 7) pin # name type description
9/88 ade3xxx pin description 84 agnd power analog ground 85 avdd18 power analog 1.8v vdd 86 avdd18 power analog 1.8v vdd 87 refr passive 1% 15.0 kohm resistor to analog ground 88 refmr passive connect to analog ground 89 refpr passive 470nf capacitor to analog ground 90 agnd power analog ground 91 agnd power analog ground 92 inr input analog video port: red channel input 93 avdd33 power analog 3.3v vdd 94 avdd33 power analog 3.3v vdd 95 refcr passive 100nf capacitor to analog ground 96 agnd power analog ground 97 avdd18 power analog 1.8v vdd 98 avdd18 power analog 1.8v vdd 99 tst_scan input connect to digital ground 100 dgnd power digital ground 101 dvdd33 power digital 3.3v vdd 102 oba7 output output port a: blue data 7 103 oba6 output output port a: blue data 6 104 oba5 output output port a: blue data 5 105 dgnd power digital ground 106 oba4 output output port a: blue data 4 107 oba3 output output port a: blue data 3 108 oba2 output output port a: blue data 2 109 oba1 output output port a: blue data 1 110 oba0 output output port a: blue data 0 111 dvdd33 power digital 3.3v vdd 112 dgnd power digital ground 113 oga7 output output port a: green data 7 114 oga6 output output port a: green data 6 115 oga5 output output port a: green data 5 116 oga4 output output port a: green data 4 117 oga3 output output port a: green data 3 118 oga2 output output port a: green data 2 119 oga1 output output port a: green data 1 120 oga0 output output port a: green data 0 121 dvdd18 power digital 1.8v vdd 122 dgnd power digital ground table 2: pin description (sheet 4 of 7) pin # name type description
pin description ade3xxx 10/88 123 dvdd18 power digital 1.8v vdd 124 dgnd power digital ground 125 dvdd33 power digital 3.3v vdd 126 ora7 output output port a: red data 7 127 ora6 output output port a: red data 6 128 ora5 output output port a: red data 5 129 ora4 output output port a: red data 4 130 ora3 output output port a: red data 3 131 ora2 output output port a: red data 2 132 ora1 output output port a: red data 1 133 ora0 output output port a: red data 0 134 dvdd33 power digital 3.3v vdd 135 dgnd power digital ground 136 ode output output data enable 137 ohs output output horizontal sync 138 oclk output output clock 139 ovs output output vertical sync 140 dvdd18 power digital 1.8v vdd 141 dgnd power digital ground 142 dvdd18 power digital 1.8v vdd 143 dgnd power digital ground 144 obb7 output output port b: blue data 7 145 obb6 output output port b: blue data 6 146 obb5 output output port b: blue data 5 147 obb4 output output port b: blue data 4 148 dvdd33 power digital 3.3v vdd 149 dgnd power digital ground 150 obb3 output output port b: blue data 3 151 obb2 output output port b: blue data 2 152 obb1 output output port b: blue data 1 153 obb0 output output port b: blue data 0 154 ogb7 output output port b: green data 7 155 ogb6 output output port b: green data 6 156 ogb5 output output port b: green data 5 157 ogb4 output output port b: green data 4 158 dvdd33 power digital 3.3v vdd 159 dgnd power digital ground 160 ogb3 output output port b: green data 3 161 ogb2 output output port b: green data 2 table 2: pin description (sheet 5 of 7) pin # name type description
11/88 ade3xxx pin description 162 ogb1 output output port b: green data 1 163 ogb0 output output port b: green data 0 164 dvdd18 power digital 1.8v vdd 165 dgnd power digital ground 166 dvdd18 power digital 1.8v vdd 167 dgnd power digital ground 168 orb7 output output port b: red data 7 169 orb6 output output port b: red data 6 170 orb5 output output port b: red data 5 171 orb4 output output port b: red data 4 172 dvdd33 power digital 3.3v vdd 173 dgnd power digital ground 174 orb3 output output port b: red data 3 175 orb2 output output port b: red data 2 176 orb1 output output port b: red data 1 177 orb0 output output port b: red data 0 178 dvdd18 power digital 1.8v vdd 179 dgnd power digital ground 180 dvdd18 power digital 1.8v vdd 181 dgnd power digital ground 182 clkout output not to be connected - reserved 183 clkin input to be connected to digital ground - reserved 184 tcon_in input tcon input 185 dvdd33 power digital 3.3v vdd 186 dgnd power digital ground 187 tcon7 input/output tcon output 7/yuv input 15 188 tcon6 input/output tcon output 6/yuv input 14 189 tcon5 input/output tcon output 5/yuv input 13 190 tcon4 input/output tcon output 4/yuv input 12 191 dvdd18 power digital 1.8v vdd 192 dgnd power digital ground 193 dvdd18 power digital 1.8v vdd 194 dgnd power digital ground 195 tcon3 input/output tcon output 3/yuv input 11 196 tcon2 input/output tcon output 2/yuv input 10 197 tcon1 input/output tcon output 1/yuv input 9 198 tcon0 input/output tcon output 0/yuv input 8 199 dvdd18 power digital 1.8v vdd 200 dgnd power digital ground table 2: pin description (sheet 6 of 7) pin # name type description
pin description ade3xxx 12/88 201 dvdd18 power digital 1.8v vdd 202 dgnd power digital ground 203 scl input i2c clock 204 sda open drain i/o i2c data 205 xclk output crystal clock buffered output 206 xclk_en input crystal clock output enable 0: xclk output disabled 1: xclk output active 207 resetn input reset input (active low) 208 yuv7 input tv video input port: data 7 table 2: pin description (sheet 7 of 7) pin # name type description
13/88 ade3xxx global control block 2 ade3xxx functional description 2.1 global control block the global control block is responsible for: l selecting clock sources l power control l i2c control l sclk frequency synthesizer control l block-by-block synchronous reset generation the global control block runs on the xclk clock domain which is required to be active for programming. the clock domains of all other blo cks are set in the global control block. for i2c access, the requested block must be driven with a valid clock above 10 mhz. clock domains are shown in figure 2 . to program the sclk frequency synthesizer to a desired frequency (fout, in mhz), the following equations apply: figure 2: clock domains table 3: sclk frequency ranges frequency range sdiv f out < 8 x f xclk and f out 3 4 x f xclk 0 f out < 4 x f xclk and f out 3 2 x f xclk 1 f out < 2 x f xclk and f out 3 f xclk 2 adc (analog) dvi rx (analog) yuv to rgb sclk freq.synth. line lock pll sync measure i2c data measure g a m m a o s d a p c o u t p u t m u x adc digital i/f scaler output sequencer ade3xxx pc analog inr, g, b v,h,csync dvi link rx0-2, rxc fm freq. synth. sync re-time p n l tcon s r g b p a t t e r n g e n . flicker detect pwm dvi decoder hdcp yuv video yuv, yuvclk global microcontroller scl, sda ora, oga, oba orb, ogb, obb oclk ode, ohs, ovs tcon dmux smux data data data s y n c s y n c inclk domain sclk domain dotclk domain xclk domain
global control block ade3xxx 14/88 md = int(f xclk x (2 (6 + ndiv - sdiv) ) / f out ) pe = int((2 15 ) x (md + 1 - f xclk x (2 (6 + ndiv - sdiv) ) / f out )) where f xclk is the external crystal frequency in mhz (typically 27). the maximum sclk frequency generated by this block is f xtal x 2 (2+ndiv) . for lower power operation, set all clock sources to the zero setting and also set the analog power disables. in this condition, only the crystal clock domain (xclk) runs and blocks in inclk or dotclk domains are not accessible by i2c. to detect a dvi plug event and wake from a low power state, program the dvi detection clock source select to the dvi detect clock and enable the analog power control for the dvi detect clock. all other clock sources are set to zero. f out < f xclk and f out 3 f xclk /2 3 f out < f xclk /2 and f out 3 f xclk /4 4 f out < f xclk /4 and f out 3 f xclk /8 5 f out < f xclk /8 and f out 3 f xclk /16 6 f out < f xclk /16 and f out 3 f xclk /32 7 table 4: global registers (sheet 1 of 4) register name addr. mode bits default description glbl_null_addr 0x0000 r/w [7:0] 0x0 chip revision id glbl_clk_src_sel_0 0x0001 [7] 0x0 reserved r/w [6:4] 0x5 dotclk source 0x0: yuvclk pin 0x1: sclk freq synth 0x2: fm freq synth (normal) 0x3: inclk 0x4: clkin pin 0x5: crystal clock 0x6: 0 0x7: reserved r/w [3:0] 0xa inclk source 0x0: yuvclk pin (yuv input) 0x1: dvi_pllclk (dvi input) 0x2: adcclock red 0x3: adcclock green 0x4: adc clock blue 0x5: sclk freq synth 0x6: dvi detect clock 0x7: llk pll (adc input) 0x8: clkin pin 0x9: fm freq synth 0xa: crystal clock 0xb: 0 0xc - 0xf: reserved table 3: sclk frequency ranges (continued) frequency range sdiv
15/88 ade3xxx global control block glbl_clk_src_sel_2 0x0002 [7] 0x0 reserved r/w [6:4] 0x4 llk ctrl clk source 0x0: yuvclk pin 0x1: sclk freq synth 0x2: llkpll control clock (normal) 0x3: clkin pin 0x4: crystal clock 0x5: 0 0x6 - 0x7: reserved [3] reserved r/w [2:0] 0x4 llk zero clk source 0x0: yuvclk pin 0x1: sclk freq synth 0x2: llkpll zero clock (normal) 0x3: clkin pin 0x4: crystal clock 0x5: 0 0x6 - 0x7: reserved glbl_clk_inv 0x0003 [7] 0x0 reserved r/w [6] 0x0 invert yuv clock r/w [5] 0x0 invert dvi detect clock r/w [4] 0x0 invert adc clock r/w [3] 0x0 invert llpll zero clock r/w [2] 0x0 invert llpll ctrl clock r/w [1] 0x0 invert dot clock r/w [0] 0x0 invert input clock glbl_ana_pwr 0x0005 [7:5] 0x0 reserved r/w [4] 0x1 blue adc power down r/w [3] 0x1 green adc power down r/w [2] 0x1 red adc power down r/w [1] 0x1 dvi detect clock power down r/w [0] 0x1 dvi pll power down glbl_xk_srst 0x0006 [7:3] 0x0 reserved r/w [2] 0x0 smeas block reset, synchronous to xclk r/w [1] 0x0 srt block reset, synchronous to xclk r/w [0] 0x0 frame sync block reset, synchronous to xclk glbl_i2c_ctrl 0x0007 [7:3] 0x0 reserved r/w [2] 0x0 disable i2c auto increment r/w [1] 0x0 sda pmos enable r/w [0] 0x0 bypass i2c filter glbl_xtal_ctrl 0x0008 [7:1] 0x0 reserved r/w [0] 0x1 crystal oscillator enable table 4: global registers (sheet 2 of 4) register name addr. mode bits default description
global control block ade3xxx 16/88 glbl_sclk_synth_ctrl 0x0009 [7:5] 0x0 reserved r/w [4:3] 0x0 xtal frequency multiplier ndiv 0x0: f xclk = 54mhz 0x1: f xclk = 27mhz (normal) 0x2: f xclk = 13.5mhz 0x3: reserved r/w [2] 0x0 sclk frequency synthesizer ext_pll (normal operation = 0) r/w [1] 0x0 sclk frequency synthesizer pll_sel (normal operation = 1) r/w [0] 0x1 sclk freq synth control disable (normal operation = 0) glbl_sclk_md_sd 0x000a r/w [7:3] 0x0 sclk frequency synthesizer md, range is [16,31] r/w [2:0] 0x0 sclk frequency synthesizer sdiv, range is [0,7] glbl_sclk_pe_l 0x000b r/w [7:0] 0x0 sclk frequency synthesizer pe, range is [0, 32767] glbl_sclk_pe_h 0x000c r/w [7:0] glbl_tst_ctrl 0x000d [7:1] 0x0 reserved r/w [0] 0x0 functional test mode enable glbl_adc_clk_src_sel [7:3] reserved r/w [2:0] 0x5 adc sample clock source 0x0: yuvclk pin 0x1: llk_pll (normal) 0x2: sclk freq synth 0x3: clkin pin 0x4: fm freq synth 0x5: crystal clock 0x6: 0 0x7: reserved glbl_sclk_ctrl 0x0010 [7:5] 0x0 reserved r/w [4] 0x0 invert sclk [3] reserved r/w [2:0] 0x0 sclk source select 0x0: yuvclk pin 0x1: sclk freq synth 0x2: fm freq synth (normal) 0x3: inclk source 0x4: clkin pin 0x5: crystal clock 0x6: 0 0x7: reserved glbl_tcon_bpad_en 0x0011 r/w [7:0] 0x0 for each bit n (0 to 7), 0: tcon[n] pin is tcon output 1: tcon[n] pin is input into tvi block table 4: global registers (sheet 3 of 4) register name addr. mode bits default description
17/88 ade3xxx fm frequency synthesizer 2.2 fm frequency synthesizer the fm frequency synthesizer creates a clock equivalent to up to eight times the crystal input clock, using a digital frequency synthesizer. the modulation period and amplitude are directly controlled by i2c registers. the i2c interface runs in the llk_ctrl clock domain, which must be active for access. the output frequency (f out ) is related to the 32-bit phase_rate and crystal frequency (f xclk ) as follows: f out = f xclk x 2 27+ndiv / phase_rate glbl_clk_src_sel_3 0x0012 [7] reserved r/w [6:4] 0x4 yuv clock source 0x0: yuvclk pin 0x1: sclk freq synth 0x2: yuvclk pin (normal) 0x3: clkin pin 0x4: crystal clock 0x5: 0 0x6 - 0x7: reserved [3] reserved r/w [2:0] 0x4 dvi detection clock source 0x0: yuvclk pin 0x1: sclk freq synth 0x2: dvi detect clock (normal) 0x3: clkin pin 0x4: crystal clock 0x5: 0 0x6 - 0x7: reserved glbl_ik_srst 0x0020 r/w [7] 0x0 hdcp block reset synchronous to inclk r/w [6] 0x0 dft block reset synchronous to inclk r/w [5] 0x0 adc block reset synchronous to inclk r/w [4] 0x0 scaler block reset synchronous to inclk r/w [3] 0x0 yuv block reset synchronous to inclk r/w [2] 0x0 dvi block reset synchronous to inclk r/w [1] 0x0 dmeas block reset synchronous to inclk r/w [0] 0x0 smux block reset synchronous to inclk glbl_dk_srst 0x0040 [7] 0x0 reserved r/w [6] 0x0 pgen block reset synchronous to dotclk r/w [5] 0x0 omux block reset synchronous to dotclk r/w [4] 0x0 apc block reset synchronous to dotclk r/w [3] 0x0 osd block reset synchronous to dotclk r/w [2] 0x0 gamma block reset synchronous to dotclk r/w [1] 0x0 osq block reset synchronous to dotclk r/w [0] 0x0 scale block reset synchronous to dotclk table 4: global registers (sheet 4 of 4) register name addr. mode bits default description
adc block ade3xxx 18/88 where f out and f xclk are in mhz. the maximum output frequency of the fm frequency synthesizer is f xtal x 2 (2+ndiv) . note that native duty cycle of the fm frequency synthesizer is not 50/50. we recommend to either enable the divide-by-two in the fm synthesizer block for frequencies up to f xclk x 2 (1+ndiv) (typically 108 mhz) or set the output mux to a double wide output mode for pixel clocks above f xclk x 2 (1+ndiv) . this will ensure a 50% duty clock on the output. 2.3 adc block the analog port consists of three 9-bit rgb adcs with preamp, gain/offset adjustment and digital filtering. the i2c interface for the adc block is in the inclk clock domain which must be active for programming. input voltage, gain and offset register settings are approximately related to the output code. in this equation, the output code (output_code_8b) is equal to: 457 x offset / 2 8 + 181 x gain x input_mv / 2 16 - 125 x gain x offset / 2 16 - 219 table 5: fm frequency synthesizer registers register name addr mode bits default description fm_fs_ctrl 0x0830 [7:4] reserved r/w [3] 0x0 clear the fm synthesizer r/w [2] 0x0 clear the fs accumulator r/w [1] 0x0 activate the frequency modulation r/w [0] 0x0 divide the output by 2 fm_fs_pr_0 0x0831 r/w [7:0] 0x8000000 phase rate fm_fs_pr_1 0x0832 r/w [7:0] fm_fs_pr_2 0x0833 r/w [7:0] fm_fs_pr_3 0x0834 r/w [7:0] fm_fs_amplitude 0x0835 r/w [7:0] 0x0 lsb = 72 ps fm_fs_periodx64 0x0836 r/w [7:0] 0x80 lsb = 1.185 s table 6: adc registers register addr. mode bits default description adc_dither 0x0324 [7] reserved r/w [6] 0x0 dither horizontally r/w [5] 0x0 dither vertically r/w [4] 0x0 dither temporally r/w [3] 0x0 force dither high r/w [2] 0x0 enable dither [1:0] reserved adc_offset_r 0x0326 r/w [7:0] 0x0 offset control, red channel adc_offset_g 0x0328 r/w [7:0] 0x0 offset control, green channel adc_offset_b 0x0329 r/w [7:0] 0x0 offset control, blue channel adc_gain_r 0x032a r/w [7:0] 0x0 gain control, red channel adc_gain_g 0x032b r/w [7:0] 0x0 gain control, green channel adc_gain_b 0x032c r/w [7:0] 0x0 gain control, blue channel
19/88 ade3xxx line lock pll block 2.4 line lock pll block the line lock pll recovers a sample clock from an incoming hsync source. the response characteristics of the line lock pll are adjustable for optimimum response time and jitter filtering. the phase of the sample clock is digitally adjustable by steps of 289 ps (with a 27- mhz crystal). the i2c interface of the line lock pll is in the llk_ctrl clock domain which must be active for programming. the pll loop filter has three ranges with independent filter parameters. when the phase detector error remains below a programmable threshold for a programmable number of input lines, the loop filter coefficients change. any phase detector error above the programmed threshold reverts the filter to the appropriate level in one line. the operation is represented in figure 3 . the digital loop filter is controlled by three parameters: mfactor, a and b. m_factor is the desired number of clocks per input line. the a and b parameters control the response of the 2nd order digital filter. a and b are composed of a linear and exponential component designated by the l and e suffix, respectively. these numbers are related to the classic 2nd order damping and natural frequency as follows: damping = al x 2 (ae-12) x sqrt(5 x m_factor / (bl x 2 be )) natural frequency = sqrt(m_factor x 5 x bl x 2 (be-34) ) figure 3: line lock pll state diagram table 7: line lock pll registers (sheet 1 of 4) register name addr mode bits default description llk_pll_clear 0x0800 [7:6] reserved r/w [5] 0x0 master reset r/w [4] 0x0 reset the pll synthetic sync r/w [3] 0x0 reset pll offset r/w [2] 0x0 reset pll accumulator r/w [1] 0x0 reset the low pass filter r/w [0] 0x0 reset the pll phase error fast slow lock more than slow_line_nb error <= slow_tol for of lines error > lock_tol error <= lock_tol for more than lock_line_nb of lines error > slow_tol
line lock pll block ade3xxx 20/88 llk_pll_ctrl 0x0801 r/w [7:6] reserved r/w [5] 0x0 0: normal 1: diagnostic mode -- pll uses only fine error r/w [4] 0x0 0: normal 1: diagnostic -- coarse error is multiplied by 2 r/w [3] 0x0 input hsync edge selection 0: rising edge 1: falling edge r/w [2] 0x0 sync on green input selection 0: composite sync (hsync pin) 1: sync on green (csync pin) r/w [1] 0x0 0: normal 1: divide pll clock by 2 r/w [0] 0x0 0: normal 1: free-running mode llk_pll_mfactor_l 0x0802 r/w [7:0] 0x0280 number of clocks in a line llk_pll_mfactor_h 0x0803 r/w [7:0] llk_pll_hperiod_l 0x0804 r/w [7:0] 0x0040 pulse width of synthetic hsync llk_pll_hperiod_h 0x0805 r/w [7:0] llk_pll_phase_rate_init_0 0x0806 r/w [7:0] 0x0 initial phase rate llk_pll_phase_rate_init_1 0x0807 r/w [7:0] f out = f xtal x 2 27+ndiv / phase_rate llk_pll_phase_rate_init_2 0x0808 r/w [7:0] llk_pll_phase_rate_init_3 0x0809 r/w [7:0] llk_pll_phase_rate_init_wr 0x080a r/w [7:1] reserved [0] when written to 1, the pll phase rate is initialized with the initial phase rate register. self clearing. llk_pll_tc_aef 0x080b [7:4] reserved r/w [3:0] 0xa fast time constant a exponent llk_pll_tc_bef 0x080c [7:4] reserved r/w [3:0] 0xa fast time constant b exponent llk_pll_tc_alf 0x080d [7:6] reserved r/w [5:0] 0x20 fast time constant a linear llk_pll_tc_blf 0x080e [7:6] reserved r/w [5:0] 0x20 fast time constant b linear llk_pll_tc_aes 0x080f [7:4] reserved r/w [3:0] 0x6 slow time constant a exponent llk_pll_tc_bes 0x0810 [7:4] reserved r/w [3:0] 0x6 slow time constant b exponent llk_pll_tc_als 0x0811 [7:6] reserved r/w [5:0] 0x20 slow time constant a linear table 7: line lock pll registers (sheet 2 of 4) register name addr mode bits default description
21/88 ade3xxx line lock pll block llk_pll_tc_bls 0x0812 [7:6] reserved r/w [5:0] 0x20 slow time constant b linear llk_pll_tc_aek 0x0813 [7:4] reserved r/w [3:0] 0x6 lock time constant a exponent llk_pll_tc_bek 0x0814 [7:4] reserved r/w [3:0] 0x6 lock time constant b exponent llk_pll_tc_alk 0x0815 [7:6] reserved r/w [5:0] 0x20 lock time constant a linear llk_pll_tc_blk 0x0816 [7:6] reserved r/w [5:0] 0x20 lock time constant b linear llk_pll_tc_slow_tol 0x0817 r/w [7:0] 0x80 more than slow_line_nb lines with a phase error less than the slow_tol will set the slow status bit, and the pll will work with the slow time constant. one or more lines with a phase error more than slow_tol will reset the slow status bit, and the pll will work with the fast time constant. lsb of slow_tol is approx. 200ps. llk_pll_tc_slow_line_nb 0x0818 r/w [7:0] 0x10 llk_pll_lock_tol 0x0819 r/w [7:0] 0x20 more than lock_line_nb lines with a phase error less than the lock_tol will set the lock status bit, and the pll will work with the lock time constant. one or more lines with a phase error more than lock_tol will reset the lock status bit, and the pll will work with the slow time constant. lsb of lock_tol is approx. 200 ps. llk_pll_lock_line_nb 0x081a r/w [7:0] 0x30 llk_pll_ph_offset 0x081b r/w [7:0] 0x0 phase adjustment. the maximum phase offset value is equal to phase_rate[31:21] or 0x40, whichever is higher. llk_pll_ph_offset_en 0x081c r/w [7] 0x0 phase enable [6:0] reserved llk_pll_pulse_high_ext 0x081d r/w [7] 0x0 0: no pulse extend 1: extend pulse (normal) [6:3] reserved r/w [2:0] 0x0 pulse extend amount 0x0: minimum 0x7: maximum (normal) llk_pll_stat_lines_l 0x081e r/w [7:0] 0x10 number of lines to statistically analyze. llk_pll_stat_lines_h 0x081f r/w [7:0] llk_pll_stat_error_inc_low 0x0820 [7:0] reserved table 7: line lock pll registers (sheet 3 of 4) register name addr mode bits default description
digital video input (dvi) ade3xxx 22/88 2.5 digital video input (dvi) the dvi receiver has the following features: l compatible with all dvi complaint transmitters up to 140 mhz pixel clock l on chip termination adjustable by i2c and/or one (~10x) external reference resistor l hdcp and standby / power down supported l decoder digitally corrects for skew errors of at least 1 pixel in reference to any other channel l bitstream can be decoded and measured without the presence of horizontal and vertical sync pulses llk_pll_update 0x0840 r [7] in free-running mode, toggles when status is updated. in one-shot mode, this bit is set when status is ready. [6:2] reserved r/w [1] 0x0 0: free-running mode 1: one-shot mode r/w [0] 0x0 update enable llk_pll_status 0x0841 [7:4] reserved r [3] llk overflow r [2] coarse error = 0 r [1] in slow mode r [0] in lock mode llk_pll_ph_error_l 0x0842 r [7:0] phase error llk_pll_ph_error_h 0x0843 r [7:0] lsb = approx. 200ps llk_pll_phase_rate_0 0x0844 r [7:0] llk phase rate llk_pll_phase_rate_1 0x0845 r [7:0] f out = f xtal x 2 27+ndiv / phase_rate llk_pll_phase_rate_2 0x0846 r [7:0] llk_pll_phase_rate_3 0x0847 r [7:0] llk_pll_phase_rate_i_0 0x0848 r [7:0] integral phase rate llk_pll_phase_rate_i_1 0x0849 r [7:0] llk_pll_phase_rate_i_2 0x084a r [7:0] llk_pll_phase_rate_i_3 0x084b r [7:0] llk_pll_stat_error_mean 0x084c r [7:0] average phase error over stat_lines phase error lsb is approx. 200ps llk_pll_stat_error_pp_l 0x084d r [7:0] peak phase error over stat_lines llk_pll_stat_error_pp_h 0x084e r [7:0] phase error lsb is approx. 200ps llk_pll_stat_error_abs_l 0x084f r [7:0] sum of absolute phase errors over stat_lines phase error lsb is approx. 200ps llk_pll_stat_error_abs_h 0x0850 r [7:0] llk_pll_stat_error_gtx 0x0851 [7:0] reserved table 7: line lock pll registers (sheet 4 of 4) register name addr mode bits default description
23/88 ade3xxx digital video input (dvi) recommended values for best receiver quality are given in the following table: table 8: recommended dvi values clock speed dvi_pll_0 dvi_pll_1 0 to 30 mhz 0x02 0x00 31 to 60 mhz 0x03 0x00 61 to 100 mhz 0x04 0x00 101 to 140 mhz 0x05 0x00 table 9: dvi registers (sheet 1 of 5) register name addr mode bits default description dvi_accum_const 0x0401 [7:4] 0x5 reserved r/w [3:0] 0x5 digital filter response speed 5: fastest 14: slowest dvi_ext_shift_cnt 0x0402 r/w [7:6] reserved r/w [5:0] 0x08 alignment position of chan0, used for debugging only dvi_ext_shift_cnt_enab 0x0403 [7:6] reserved r/w [6] 0x0 0: normal 1: freeze alignment readout r/w [5:0] 0x0 initial value for the alignment position for all channels dvi_invalid_l 0x0404 invalid code count for left position. r [7:3] 0x0 exponent r [2:0] 0x0 mantissa count = (mant+8) * 2 (exp-4) , if exp>3, else count = mant dvi_invalid_c 0x0405 invalid code count for center position. r [7:3] 0x0 exponent r [2:0] 0x0 mantissa count = (mant+8) * 2 (exp-4) , if exp>3, else count = mant dvi_invalid_r 0x0406 invalid code count for right position. r [7:3] 0x0 exponent r [2:0] 0x0 mantissa count = (mant+8) * 2 (exp-4) , if exp>3, else count = mant
digital video input (dvi) ade3xxx 24/88 dvi_invalid_sel_en 0x0407 r/w [7:3] reserved r/w [2:1] 0x0 channel to count invalid code events 0: blue channel 1: green channel 2: red channel r/w [0] 0x0 invalid code accumulation period 0: 16k lines 1: 4 lines dvi_error_skew_en 0x0408 r/w [7:3] 0x0 reserved r/w [2] 0x0 0: tracking in data & blanking 1: tracking only in blanking r/w [1] 0x0 enable channel skew protection r/w [0] 0x0 enable error concealment dvi_lcr0_1 0x0409 r/w [7:4] 0x7 4 bit incr value (2s complement) r/w [3:0] 0x4 4 bit incr value (2s complement) dvi_lcr2_3 0x040a r/w [7:4] 0x0 4 bit incr value (2s complement) r/w [3:0] 0x0 4 bit incr value (2s complement) dvi_lcr4_5 0x040b r/w [7:0] 0x0 4 bit incr value (2s complement) r/w [3:0] 0x9 4 bit incr value (2s complement) dvi_lcr6_7 0x040c r/w [7:0] 0xf 4 bit incr value (2s complement) r/w [3:0] 0x0 4 bit incr value (2s complement) dvi_lcr_rv_en 0x040d r/w [7] 0x1 enable restoring force for lcr7. r/w [6] 0x0 enable restoring force for lcr6. r/w [5] 0x0 enable restoring force for lcr5. r/w [4] 0x0 enable restoring force for lcr4. r/w [3] 0x0 enable restoring force for lcr3. r/w [2] 0x0 enable restoring force for lcr2. r/w [1] 0x0 enable restoring force for lcr1. r/w [0] 0x0 enable restoring force for lcr0. dvi_test_sel 0x040e [7:0] 0x0 reserved dvi_pll_0 0x0480 r/w [7] 0x0 termination control 0: 50ohm impedance (normal) 1: high impedance table 9: dvi registers (sheet 2 of 5) register name addr mode bits default description
25/88 ade3xxx digital video input (dvi) dvi_pll_0 0x0480 r/w [7] reserved, must be set to 0 r/w [6:5] 0x0 amplifier current 0x0: 25ua (default) 0x1: 75ua 0x2: 125ua 0x3: 175ua (fastest) r/w [4:3] 0x0 vtol range overlap 0x0: 34.1ua (default) 0x1: 50.9ua 0x2: 26.0ua 0x3: 42.9ua r/w [2:0] 0x0 change pump current select 0x0: 25ua (default) 0x1: 50ua 0x2: 75ua 0x3: 100ua 0x4: 125ua 0x5: 150ua 0x6: 175ua 0x7: 200ua (fastest) dvi_pll_1 0x0481 r/w [7] 0x0 bias select 0: internal (default) 1: external r/w [6:5] 0x0 range checking interval 0x0: clk/512 (default) 0x1: clk/1024 0x2: clk/2048 0x3: clk/256 r/w [4:1] 0x0 manual range select 0x0: reserved 0x1: force range 1 (lowest) 0x2 - 0x3: force range 2 0x4 - 0x7: force range 3 0x8 - 0xf: force range 4 (highest) [0] 0x0 pll range control 0: auto (default) 1: manual dvi_pll_2 0x0482 r/w [7:6] 0x0 strobe 3 adjust 0: normal 1: slower 2: faster 3: reserved r/w [5:4] 0x0 strobe 2 adjust r/w [3:2] 0x0 strobe 1 adjust r/w [1:0] 0x0 global strobe adjust 0: normal 1: slower 2: faster 3: reserved table 9: dvi registers (sheet 3 of 5) register name addr mode bits default description
digital video input (dvi) ade3xxx 26/88 dvi_pll_3 0x0483 r/w [7:6] 0x0 strobe 7 adjust r/w [5:4] 0x0 strobe 6 adjust r/w [3:2] 0x0 strobe 5 adjust r/w [1:0] 0x0 strobe 4 adjust dvi_pll_4 0x0484 r/w [7:6] 0x0 strobe 11 adjust r/w [5:4] 0x0 strobe 10 adjust r/w [3:2] 0x0 strobe 9 adjust r/w [1:0] 0x0 strobe 8 adjust dvi_pll_5 0x0485 r/w [7:6] 0x0 strobe 15 adjust r/w [5:4] 0x0 strobe 14 adjust r/w [3:2] 0x0 strobe 13 adjust r/w [1:0] 0x0 strobe 12 adjust dvi_pll_6 0x0486 r/w [7:6] 0x0 strobe 19 adjust r/w [5:4] 0x0 strobe 18 adjust r/w [3:2] 0x0 strobe 17 adjust r/w [1:0] 0x0 strobe 16 adjust dvi_pll_7 0x0487 r/w [7:6] 0x0 strobe 23 adjust r/w [5:4] 0x0 strobe 22 adjust r/w [3:2] 0x0 strobe 21 adjust r/w [1:0] 0x0 strobe 20 adjust dvi_pll_8 0x0488 r/w [7:6] 0x0 strobe 27 adjust r/w [5:4] 0x0 strobe 26 adjust r/w [3:2] 0x0 strobe 25 adjust r/w [1:0] 0x0 strobe 24 adjust dvi_pll_2 0x0482 r/w [7:6] [5:4] [3:2] [1:0] 0x0 strobe [0:3] delay adjustment 0x0: normal 0x1: slow 0x2: fast 0x3: reserved dvi_pll_3 0x0483 r/w [7:6] [5:4] [3:2] [1:0] 0x0 strobe [4:7] delay adjustment 0x0: normal 0x1: slow 0x2: fast 0x3: reserved dvi_pll_4 0x0484 r/w [7:6] [5:4] [3:2] [1:0] 0x0 strobe [8:11] delay adjustment 0x0: normal 0x1: slow 0x2: fast 0x3: reserved dvi_pll_5 0x0485 r/w [7:6] [5:4] [3:2] [1:0] 0x0 strobe [12:15] delay adjustment 0x0: normal 0x1: slow 0x2: fast 0x3: reserved table 9: dvi registers (sheet 4 of 5) register name addr mode bits default description
27/88 ade3xxx hdcp block 2.6 hdcp block the hdcp block implements the datapath decryption block of the hdcp content protection scheme of dvi. please refer to the hdcp specification 1.0 for details. the state machines of the hdcp specification are split between the external microcontroller and this block. only the high speed and data intensive cryptographic functions are implemented in this block to maintain maximum system level flexibility. dvi_pll_6 0x0486 r/w [7:6] [5:4] [3:2] [1:0] 0x0 strobe [16:19] delay adjustment 0x0: normal 0x1: slow 0x2: fast 0x3: reserved dvi_pll_7 0x0487 r/w [7:6] [5:4] [3:2] [1:0] 0x0 strobe [20:23] delay adjustment 0x0: normal 0x1: slow 0x2: fast 0x3: reserved dvi_pll_8 0x0488 r/w [7:6] [5:4] [3:2] [1:0] 0x0 strobe [24:27] delay adjustment 0x0: normal 0x1: slow 0x2: fast 0x3: reserved dvi_pll_9 0x0489 [7:6] reserved r/w [5] 0x0 test enable (normal operation = 0) r/w [4] 0x0 strobe delay adjustment step 0: 45ps (default) 1: 72ps r/w [3:2] 0x0 strobe 29 adjust 0: normal 1: slower 2: faster 3: reserved r/w [1:0] 0x0 strobe 28 adjust r/w [3:2] [1:0] 0x0 strobe [28:29] delay adjustment 0x0: normal 0x1: slow 0x2: fast 0x3: reserved dvi_pll_10 0x048a [7] reserved r [6:4] test output dvipll[79:77] r [3:0] pll range status r [3:0] 0x0 pll range status table 9: dvi registers (sheet 5 of 5) register name addr mode bits default description
hdcp block ade3xxx 28/88 table 10: hdcp registers register name addr mode bits default description hdcp_status 0x0500 [7:3] 0x0 reserved r [2:0] 0x0 decrypt state machine 0x0: idle 0x1: frame key recalc 0x2: data 0x3: unknown blank 0x4: horizontal blank 0x5: vertical blank 0x6-0x7: reserved hdcp_ctrl 0x0501 r/w [7:6] 0x0 vsync selection 0x0: in_vsync 0x1: in_venab falling edge 0x2: in_venab rising edge 0x3: in_vsync falling edge r/w [5:4] 0x0 hsync selection 0x0: in_hsync 0x1: in_enab falling edge 0x2: in_enab rising edge 0x3: in_hsync falling edge r/w [2] 0x0 bypass hdcp block r/w [1] 0x0 authentication ok from mcu r/w [0] 0x0 0: state machine standby 1: trigger an authentication cycle hdcp_an0 0x0502 r/w [7:0] 0x0 an hdcp_an1 0x0503 r/w [7:0] hdcp_an2 0x0504 r/w [7:0] hdcp_an3 0x0505 r/w [7:0] hdcp_an4 0x0506 r/w [7:0] hdcp_an5 0x0507 r/w [7:0] hdcp_an6 0x0508 r/w [7:0] hdcp_an7 0x0509 r/w [7:0] hdcp_km0 0x050a r/w [7:0] 0x0 kn hdcp_km1 0x050b r/w [7:0] hdcp_km2 0x050c r/w [7:0] hdcp_km3 0x050d r/w [7:0] hdcp_km4 0x050e r/w [7:0] hdcp_km5 0x050f r/w [7:0] hdcp_km6 0x0510 r/w [7:0] hdcp_r_l 0x0511 r/w [7:0] 0x0 r hdcp_r_h 0x0512 r/w [7:0]
29/88 ade3xxx yuv block 2.7 yuv block the tv video input module is used to interface external tv video decoder chip. it handles vesa video interface port(vip) 8-bit/16-bit yc b c r , vmi/ itu-r recommendation 656 (ccir656) yc b c r and double clock edge input rgb data formats. it extracts embedded sync timing and converts data into rgb color space. all the functions in this module are controlled by the system microcontroller through i2c registers. the following table describes the different pin configurations for yuv/rgb digital input. x = dont care mode yuv[7:0] tcon[3:0] tcon[7:4] ccir656 data[7:0] x x vmi data[7:0] x {href, vref, vactive, x} vip 8b data[7:0] x x vip 16b data[7:0] data[11:8] data[15:12] rgb posedge blue[7:0] green[3:0] {hsync,vsync,de,x} rgb negedge {red[3:0],green[7:4]} red[7:4] {hsync,vsync,de,x} table 11: yuv registers (sheet 1 of 2) register name addr mode bits default description yuv_ctrl 0x0700 [7:6] reserved r/w [5] 0x0 0: rising edge of clock 1: falling edge of clock r/w [4] 0x0 input source of color space converter 0: yuv pins 1: adc r/w [3] 0x0 color space converter enable r/w [2] 0x0 sync decoder enable r/w [1] 0x0 sample input data rate 0:1x 1: 2x r/w [0] 0x0 status reset yuv_status 0x0701 [7] reserved r/w [6] 0x0 sav detected r/w [5] 0x0 eav detected r/w [4] 0x0 anc detected r/w [3] 0x0 task detected r/w [2] 0x0 fieldid detected r/w [1] 0x0 hsync detected r/w [0] 0x0 vsync detected writing to this register will clear all bits.
sync retiming block ade3xxx 30/88 2.8 sync retiming block the sync retiming (srt) block retimes incoming synchronization signals (h sync, v sync, etc) into the xclk and inclk domains. for the xclk domain, srt has the following functionality: l retimes all sync signals going to smeas into the xclk domain. l extracts vertical sync from composite sync signals (ahsync and acsync pins) l divides clocks by 1024 for activity detection purposes. l generates a delay-filtered version of vertical sync from a mux-selectable vertical sync source. l generates a coast signal in the xclk domain for the llpll. yuv_int 0x0702 [7:6] reserved r/w [5] 0x0 0: vip 8b mode 1: vip 16b mode (skip 1 clock after every 6 valid data) r/w [4:2] 0x0 yuv data input format 0x2: yuv 16-bit 0x4: yuv 8-bit 0x6: rgb all others: reserved r/w [1] 0x0 0: c-y 1: y-c r/w [0] 0x0 0: cr-cb 1: cb-cr table 12: sync retiming registers (sheet 1 of 2) register name addr mode bits default description srtxk_csync_inv 0x01e0 [7:3] 0x0 reserved r/w [2] 0x0 invert filtered vert sync signal r/w [1] 0x0 invert composite sync signal r/w [0] 0x0 invert sog signal srtxk_sog_thr_l 0x01e1 r/w [7:0] 0x080 sog vert sync extractor threshold [7:0] srtxk_sog_thr_h 0x01e2 r/w [7:4] reserved [3:0] sog vert sync extractor threshold [11:8] srtxk_csync_thr_l 0x01e3 r/w [7:0] 0x080 composite sync vertical sync extractor threshold [7:0] srtxk_csync_thr_h 0x01e4 r/w [7:4] reserved [3:0] composite sync vertical sync extractor threshold [11:8] table 11: yuv registers (sheet 2 of 2) register name addr mode bits default description
31/88 ade3xxx sync retiming block srtxk_vsync_sel 0x01e5 r/w [7:3] reserved [2:0] 0x0 filtered vert sync source select 0x0: avsync pin 0x1: vsync from composite ahsync pin 0x2: vsync from composite acsync pin 0x3: reserved 0x4: dvi vsync 0x5: yuv vsync 0x6 - 0x7: reserved srtxk_vsync_thr_l 0x01e6 r/w [7:0] 0x080 filtered vert sync delay [7:0] srtxk_vsync_thr_h 0x01e7 r/w [7:4] reserved r/w [3:0] filtered vert sync delay [11:8] srtxk_coast_vs_sel 0x01e8 [7:4] 0x0 reserved r/w [3] 0x0 coast signal trigger edge 0: posedge of selected vertical 1: negedge of selected vertical r/w [2:0] 0x0 source select for coast vert sync trigger 0x0: avsync pin 0x1: vsync from ahsync pin 0x2: vsync from acsync pin 0x3: reserved 0x4: dvi vsync 0x5: yuv vsync 0x6: srt vsync (filtered vsync) 0x7: reserved srtxk_coast_rise_l 0x01e9 r/w [7:0] 0x0 rising edge of coast, in xclks from vsync trigger srtxk_coast_rise_m 0x01ea r/w [7:0] 0x0 srtxk_coast_rise_h 0x01eb r/w [7:0] 0x0 srtxk_coast_fall_l 0x01ec r/w [7:0] 0x0 falling edge of coast, in xclks from vsync trigger srtxk_coast_fall_m 0x01ed r/w [7:0] 0x0 srtxk_coast_fall_h 0x01ee r/w [7:0] 0x0 srtik_hs_ctrl 0x01f0 [7:3] 0x0 reserved r/w [2] 0x0 resample clock edge to transfer hsync into the inclk domain; depends on llk phase offset value. 0: posedge inclk 1: negedge inclk r/w [1:0] 0x0 horz sync source select for resampling into the inclk domain 0x0: llpll lock sync (normal) 0x1: ahsync pin 0x2: acsync pin 0x3: reserved srtik_vs_sel 0x01f1 [7:2] 0x0 reserved r/w [1:0] 0x0 vert sync source select for resampling 0x0: avsync pin 0x1: vsync from ahsync pin 0x2: vsync from acsync pin 0x3: srt vsync (filtered vsync) table 12: sync retiming registers (sheet 2 of 2) register name addr mode bits default description
sync measurement block ade3xxx 32/88 2.9 sync measurement block the input sync measurement block (smeas) continuously detects activity from all video sources. the module can measure the characteristics of the sync signals on any input port. the sync measurement module reports the results of the measurements to the system microcontro ller. this portion of the sync measurement is fully synchronous on the crystal clock (xclk). another block, the sync retiming block (srt), handles the asynchronous signal transfer of the incoming sync signals. input sync functions: l activity detection l sync management l measurement table 13: sync measurement registers (sheet 1 of 8) register name addr mode bits default description smeas_act_ctrl 0x0100 [7:4] 0x0 reserved r/w [3] 0x0 enable activity detection in free-running mode. r/w [2] 0x0 freeze results in free-running mode. no meaning in one-shot mode. 0: do not freeze the results. new result will be available on the next and subsequent toggle of the polling bit. 1: freeze the current results. the polling bit will still toggle and the block continues to free run; however, results will not be updated. r/w [1] 0x0 activity detection start. in one-shot mode it triggers the start of a measurement and is reset to zero when the measurement is complete. r/w [0] 0x0 activity detection mode control 0: free run 1: one shot smeas_act_h_smptm_l 0x0101 r/w [7:0] 0x0 sample time value for clock or hsync activity. in units of xclk_period*256 smeas_act_h_smptm_h 0x0102 r/w [7:0] 0x0 smeas_act_v_smptm_l 0x0103 r/w [7:0] 0x0 sample time value for vsync activity in units of xclk_period*256. note: this number must be larger than hsync sample time. smeas_act_v_smptm_h 0x0104 r/w [7:0] 0x0 smeas_act_h_minedge 0x0105 r/w [7:0] 0x0 minimum edge count value for clk or hsync activity. smeas_act_v_minedge 0x0106 r/w [7:0] 0x0 minimum edge count value for vsync activity. smeas_h_tmot_l 0x0107 r/w [7:0] 0x4000 timeout counter value for clk or horizontal measurement in xclks smeas_h_tmot_h 0x0108 r/w [7:0] smeas_v_tmot_l 0x0109 r/w [7:0] 0x1600 timeout counter value for vertical measurement in units of xclk/256 smeas_v_tmot_h 0x010a r/w [7:0]
33/88 ade3xxx sync measurement block smeas_clear 0x0110 [7:3] reserved r/w [2] 0x0 clear sticky status bits r/w [1] 0x0 clear all out-of-range event counters r/w [0] 0x0 clear all result registers smeas_h_ctrl 0x0111 [7] 0x0 reserved r/w [6] 0x0 enable hsync filter all hsync pulses less than smeas_filter_hs_width will be ignored. r/w [5] 0x0 measure hsync in the absence of vsync r/w [4] 0x0 enable horizontal measurement in free- running mode r/w [3] 0x0 horizontal event edge select 0: positive edge 1: negative edge r/w [2] 0x0 freeze horizontal measurements results during free-running mode. no meaning in one-shot mode. 0: do not freeze measurement results. new result will be available on the next and subsequent toggle of the polling bit. 1: freeze the current results. the polling bit will still toggle and the block continues to free run; however, results will not be updated. r/w [1] 0x0 horizontal measurement start in one-shot mode, this bit triggers the start of a measurement. the bit is reset to zero when the measurement is complete. r/w [0] 0x0 horizontal measurement mode 0: free-running 1: one-shot table 13: sync measurement registers (sheet 2 of 8) register name addr mode bits default description
sync measurement block ade3xxx 34/88 smeas_v_ctrl 0x0112 [7] 0x0 reserved r/w [6] 0x0 enable interlace measurement r/w [5] 0x0 measure odd frame from yuv only. applies only if the odd signal from yuv is present. the results in smeas_xclks_per_h and smeas_h_per_v are updated for odd frames if this bit is set. r/w [4] 0x0 enable vertical measurement in free- running mode. r/w [3] 0x0 vertical event edge select 0: positive edge 1: negative edge r/w [2] 0x0 freeze vertical measurement results in free-running mode. no meaning in one-shot mode. 0: do not freeze the results. new result will be available on the next and subsequent toggle of the polling bit. 1: freeze the current results in free-running mode. the polling bit will still toggle and the block continues to free run; however, results will not be updated. r/w [1] 0x0 vertical measurement start. in one-shot mode, this bit triggers the start of a measurement. the bit is reset to zero when the measurement is complete. r/w [0] 0x0 vertical measurement mode 0: free-running 1: one-shot smeas_h_sel 0x0113 r/w [7:4] reserved [3:0] 0x0 select a horizontal sync, enable or clock for measurement. 0x0: analog hsync 0x1: hsync generated from llpll 0x2: sog from csync pin 0x3: dvi hsync 0x4: yuv hsync 0x5: dvi data enable 0x6: yuv data enable 0x7: dviclk div1k 0x8: yuvclk div1k 0x9: tcon hsync 0xa: tcon data enable 0xb: inclk div1k 0xc: dotclk div1k 0xd-0xf: reserved table 13: sync measurement registers (sheet 3 of 8) register name addr mode bits default description
35/88 ade3xxx sync measurement block smeas_v_sel 0x0114 r/w [7:4] 0x0 selects a vertical signal for measurement of the high pulse width. 0x0: analog vsync 0x1: composite vsync 0x2: sog vsync 0x3: dvi vsync 0x4: yuv vsync 0x5: yuv vert enab (locally generated) 0x6: dvi vert enab (locally generated) 0x7: tcon vsync 0x8 - 0xf: reserved r/w [3:0] 0x0 selects a vertical signal for measurement of period and polarity. 0x0: analog vsync 0x1: composite vsync 0x2: sog vsync 0x3: dvi vsync 0x4: yuv vsync 0x5: yuv vert enable (locally generated) 0x6: dvi vert enable (locally generated) 0x7: tcon vsync smeas_status_mask 0x0119 r/w [7] 0x0 mask bit for hsync polarity check 0: ignore 1: check r/w [6] 0x0 mask bit for vsync polarity check 0: ignore 1: check [5:4] reserved r/w [3] 0x0 mask bit for vert pulse width check 0: ignore 1: check r/w [2] 0x0 mask bit for h per v check 0: ignore 1: check r/w [1] 0x0 mask bit for h period check 0: ignore 1: check r/w [0] 0x0 mask bit for v period check 0: ignore 1: check smeas_h_num_lines 0x011a r/w [7:0] 0x0 number of lines to measure for horizontal period. valid range is 1 to 255. smeas_h_skip_l 0x011b r/w [7:0] 0x0 number of lines to skip before starting a horizontal measurement. the skip counter counts from the chosen vertical source and edge. [7:0] smeas_h_skip_h 0x011c r/w [7:4] reserved [3:0] number of lines to skip before starting a horizontal measurement. the skip counter counts from the chosen vertical source and edge. [11:8] table 13: sync measurement registers (sheet 4 of 8) register name addr mode bits default description
sync measurement block ade3xxx 36/88 smeas_skew_ctrl 0x011d [7:3] 0x0 reserved r/w [2] 0x0 1 = delay vsync a number of xclks specified in smeas_delay_vsync [1] 0x0 reserved r/w [0] 0x0 write a rising edge to start the hv-skew measurement. smeas_skew_thres 0x011e r [7:0] 0x5 test skew limit in xclks. if the skew is less than this test limit, the smease_skew_status register will report an error condition. smeas_delay_vsync should be reprogrammed until the skew is large enough to prevent vcount ambiguity. smeas_delay_vsync 0x011f r/w [7:0] 0x3 number of xclks to delay vsync. smeas_ref_xk_per_h_l 0x0120 r/w [7:0] 0x0 reference value for xclks per horizontal event actual value = programmed value + 1 smeas_ref_xk_per_h_m 0x0121 r/w [7:0] 0x0 smeas_ref_xk_per_h_h 0x0122 r/w [7:0] 0x0 smeas_ref_xk_per_v_l 0x0123 r/w [7:0] 0x0 reference value for xclks per vertical event actual value = programmed value + 2 smeas_ref_xk_per_v_m 0x0124 r/w [7:0] 0x0 smeas_ref_xk_per_v_h 0x0125 r/w [7:0] 0x0 smeas_ref_h_per_v_l 0x0126 r/w [7:0] 0x0 reference value for horizontal events per vertical event smeas_ref_h_per_v_h 0x0127 r/w [7:0] 0x0 smeas_ref_xk_v_per_hi_l 0x0128 r/w [7:0] 0x0 reference value for vertical pulse width measurement result in xclks. actual value = programmed value + 1 smeas_ref_xk_v_per_hi_m 0x0129 r/w [7:0] 0x0 smeas_ref_xk_v_per_hi_h 0x012a r/w [7:0] 0x0 smeas_ref_polarity 0x012b [7:2] 0x0 reserved r/w [1] 0x0 reference value for hsync polarity. 0: active low 1: active high r/w [0] 0x0 reference value for vsync polarity. 0: active low 1: active high smeas_xk_htol_exp 0x012c r/w [7:4] 0x0 reserved [3:0] 0x0 horizontal tolerance; +/- 2 n xclks smeas_xk_vtol_exp 0x012d [7:4] 0x0 reserved r/w [3:0] 0x0 vertical tolerance; +/- 2 n xclks smeas_hsync_vtol 0x012e [7:4] 0x0 reserved r/w [3:0] 0x0 horizontal per vertical tolerance, +/- 2 n smeas_filtr_hs_width 0x012f r/w [7:0] 0x1 refer to register 0x0111 smeas_act_polling 0x013f [7:1] 0x0 reserved r [0] 0x0 toggle on activity status update in free- running mode. no function in one-shot mode. table 13: sync measurement registers (sheet 5 of 8) register name addr mode bits default description
37/88 ade3xxx sync measurement block smeas_ana_act 0x0140 [7:5] 0x0 reserved r [4] 0x0 composite sync is active r [3] 0x0 vsync from sog separator is active r [2] 0x0 comp vsync from composite sync separator is active r [1] 0x0 analog hsync is active r [0] 0x0 analog vsync is active smeas_dvi_act 0x0141 [7:2] 0x0 reserved r [1] 0x0 dvi enable is active r [0] 0x0 dvi clk / 1k is active smeas_yuv_act 0x0142 [7:5] 0x0 reserved r [4] 0x0 tcon vsync is active. r [3] 0x0 tcon hsync is active. r [2] 0x0 tcon enable is active. r [1] 0x0 yuv enable is active. r [0] 0x0 yuv clk / 1k is active. smeas_ana_stuck 0x0143 [7:5] 0x0 reserved r [4] 0x0 comp sync is stuck at 1(high)/0(low) r [3] 0x0 vsync from sog separator is stuck at 1(high)/0(low) r [2] 0x0 comp vsync from separator is stuck at 1(high)/0(low) r [1] 0x0 analog hsync is stuck at 1(high)/0(low) r [0] 0x0 analog vsync is stuck at 1(high)/0(low) smeas_dvi_stuck 0x0144 [7:2] 0x0 reserved r [1] 0x0 dvi data enable is stuck at 1(high)/0(low) r [0] 0x0 dvi clk / 1k is stuck at 1(high)/0(low) smeas_yuv_stuck 0x0145 r [7:5] 0x0 reserved r [4] 0x0 tcon vsync is stuck at 1(high)/0(low) r [3] 0x0 tcon hsync is stuck at 1(high)/0(low) r [2] 0x0 tcon data enable is stuck at 1(high)/0(low) r [1] 0x0 yuv data enable is stuck at 1(high)/0(low) r [0] 0x0 yuv clk / 1k is stuck at 1(high)/0(low) smeas_xk_per_h_l 0x0146 r [7:0] 0x0 xclks per horizontal event - 1 smeas_xk_per_h_m 0x0147 r [7:0] 0x0 smeas_xk_per_h_h 0x0148 r [7:0] 0x0 smeas_xk_per_v_l 0x0149 r [7:0] 0x0 xclks per vertical event - 1 smeas_xk_per_v_m 0x014a r [7:0] 0x0 smeas_xk_per_v_h 0x014b r [7:0] 0x0 table 13: sync measurement registers (sheet 6 of 8) register name addr mode bits default description
sync measurement block ade3xxx 38/88 smeas_h_per_v_l 0x014c r [7:0] 0x0 horizontal events per vertical event smeas_h_per_v_h 0x014d r [7:0] 0x0 smeas_sk_v_hi_l 0x014e r [7:0] 0x0 vertical high time in xclks - 1 smeas_sk_v_hi_m 0x014f r [7:0] 0x0 smeas_sk_v_hi_h 0x0150 r [7:0] 0x0 smeas_timeout_status 0x0151 [7:2] 0x0 reserved r [1] 0x0 indicates that the horizontal measurement timed out. r [0] 0x0 indicates that the vertical measurement timed out. smeas_status_range 0x0152 r [7] 0x0 in free-running mode any of the status bits can change at the end of each measurement. in one-shot mode any of the status bits can change at the completion of the measurement. the meas_sticky_status bit is a bitwise or of bits[3:0] (before the bitwise or, the mask in smeas_status_mask is and in) and is sticky. the only way to reset it is for software to write a zero into this bit. this bit goes to the scaler to blank the scaler output. a write to this reg will reset it to 0. r [6] 0x0 indicates that one of the measured polarities does not match the reference value. r [5] 0x0 hsync (selected by smeas_h_sel) polarity. 0: active low 1: active high r [4] 0x0 vsync (selected by smeas_v_sel) polarity. 0: active low 1: active high r [3] 0x0 indicates that the vertical pulse width measurement exceeded the reference +/- tolerance range. r [2] 0x0 indicates that the horizontal per vertical measurement exceeded the reference +/- tolerance range. r [1] 0x0 indicates that the xclks per horizontal measurement exceeded the reference +/- tolerance range. r [0] 0x0 indicates that the xclks per vertical measurement exceeded the reference +/- tolerance range. smeas_meas_polling 0x0153 [7:2] 0x0 reserved r [1] 0x0 toggle on h meas free-running mode, at end of each meas. no function on one-shot mode. r [0] 0x0 toggle on v meas free-running mode, at end of each meas. no function on one-shot mode. table 13: sync measurement registers (sheet 7 of 8) register name addr mode bits default description
39/88 ade3xxx sync measurement block smeas_skew_status 0x0154 [7:2] 0x0 reserved r [1] 0x0 0: hsync to vsync skew above threshold 1: hsync to vsync skew below theshold r [0] 0x0 0: skew measurement running 1: skew measurement finished smeas_v_outof_rng 0x0155 r [7:0] 0x0 the number of times the xclks per vertical reference/meas comparison has been out of range. maximum is 240. clear by setting smeas_clear[1]. smeas_h_outof_rng 0x0156 r [7:0] 0x0 the number of times the xclks per horizontal reference/meas comparison has been out of range. maximum is 240. clear by setting smeas_clear[1]. smeas_hv_outof_rng 0x0157 r [7:0] 0x0 the number of times the horizontal per vertical reference/meas comparison has been out of range. maximum is 240. clear by setting smeas_clear[1]. smeas_vhi_outof_rng 0x0158 r [7:0] 0x0 the number of times the vertical pulse width in xclks reference/meas comparison has been out of range. maximum is 240. clear by setting smeas_clear[1]. smeas_hpol_outof_rng 0x0159 r [7:0] 0x0 the number of times the horizontal polarity reference/meas comparison has been out of range. maximum is 240. clear by setting smeas_clear[1]. smeas_vpol_outof_rng 0x015a r [7:0] 0x0 the number of times the vertical polarity reference/meas comparison has been out of range. maximum is 240. clear by setting smeas_clear[1]. table 13: sync measurement registers (sheet 8 of 8) register name addr mode bits default description
sync mux block ade3xxx 40/88 2.10 sync mux block the sync mux (smux) block provides the following functions: l selects between all possible sync signals l generates missing sync signals l selects between original and generated signals for output l generates the clamp signal for the adc table 14: sync mux registers (sheet 1 of 2) register name addr mode bits default description smux_ctrl0 0x0200 r/w [7] 0x0 select tcon[7] as internal_hsync source. overrides smux_ctrl0[1:0] selection. r/w [6] 0x0 select tcon[6] as internal_vsync source. overrides smux_ctrl0[3:2] selection. r/w [5] 0x0 select tcon[5] as internal_enable source. overrides smux_ctrl0[4] selection. r/w [4] 0x0 internal_enab select 0: dvi 1: yuv r/w [3:2] 0x0 vsync_internal select 0x0: dvi 0x1: srt vsync (normally analog) 0x2: yuvi 0x3: composite sync decoder r/w [1:0] 0x0 hsync_internal select 0x0: dvi 0x1: llk hsync (normally analog) 0x2: yuvi 0x3: raw vga hsync (may have jitter) smux_ctrl1 0x0201 [7:6] 0x0 reserved r/w [5] 0x0 vsync_out invert r/w [4] 0x0 hsync_out invert r/w [3] 0x0 v_reference edge select 0: falling 1: rising r/w [2] 0x0 v_reference select 0: venab_generated 1: vsync_internal r/w [1] 0x0 h_reference edge select 0: falling 1: rising r/w [0] 0x0 h_reference select 0: enab_internal 1: hsync_internal
41/88 ade3xxx sync mux block smux_ctrl2 0x0202 r [7] 0x0 v_reference toggle output r/w [6] 0x0 software odd set (for testing odd params on the bench) r/w [5:4] 0x0 odd_out select 0x0: yuv 0x1: v_reference toggle 0x2: smux_ctrl2[6] 0x3: reserved r/w [3] 0x0 valid_out select 0: yuv 1: valid_generated r/w [2] 0x0 enab_out select 0: enab_internal 1: enab_generated r/w [1] 0x0 vsync_out select 0: vsync_internal 1: hsync_generated r/w [0] 0x0 hsync_out select 0: hsync_internal 1: hsync_generated smux_clamp_set_l 0x0203 r/w [7:0] 0x0 adc clamp signal rising edge [11:0], relative to selected horizontal reference signal, in inclks (pixels) smux_clamp_set_h 0x0204 r/w [3:0] 0x0 smux_clamp_rst_l 0x0205 r/w [7:0] 0x0 adc clamp falling edge [11:0] smux_clamp_rst_h 0x0206 r/w [3:0] 0x0 smux_henab_set_l 0x0207 r/w [7:0] 0x0 horizontal enable start [11:0] (left edge of image) relative to the selected horizontal reference edge in inclks (pixels)) smux_henab_set_h 0x0208 r/w [3:0] 0x0 smux_henab_rst_l 0x0209 r/w [7:0] 0x0 horizontal enable end [11:0] smux_henab_rst_h 0x020a r/w [3:0] 0x0 smux_venab_set_l 0x020b r/w [7:0] 0x0 vertical enable start [11:0] (top edge of image) relative to the selected vertical reference edge (in lines) smux_venab_set_h 0x020c r/w [3:0] 0x0 smux_venab_rst_l 0x020d r/w [7:0] 0x0 vertical enable end smux_venab_rst_h 0x020e r/w [3:0] 0x0 smux_hsync_phase 0x020f r/w [7:0] 0x0 number of horizontal pixels/inclks that the generated hsync edge is from the horizontal reference edge. 2s complement [-128,127] smux_vsync_phase 0x0210 r/w [7:0] 0x0 number of vertical lines that the generated vsync edge is from the vertical reference edge. 2s complement [-128,127] table 14: sync mux registers (sheet 2 of 2) register name addr mode bits default description
data mux block ade3xxx 42/88 2.11 data mux block data mux provides the following functions: l selection of one among three data sources l debug modes (e.g. bit order swap, color swap) 2.12 data measurement block the data measurement module measures several characteristics of the data and sync signals. data measurements are taken over a programmable window as defined by an upper left (mix_x, min_y) and a lower right (max_x, max_y), which may be the whole frame. measurements are programmable either per color channel or over all color channels. this module computes all measurements of sync and data format that are done in the inclk domain. the sync measurement module does measurements in the xclk domain. the inclks per de measurement does not use the window feature. it measures the number of inclk per de and returns the result for every line. all unused or reserved bits return as zero. windows are relative to sync pulses. a window defined from (0,0) - (0xfff, 0xfff) goes from sync to sync. the reference edge to use, rising or falling, is also programmable per x and y coordinates. configure smux to provide a positive polarity sync to the dmeas block. all window enables reset at 0 and always reset on the rising or falling edge of sync. see the description of the specific phm and dmm measurements performed within dmeas here below. most algorithms are run over separate or all color channels. most algorithms also contain a threshold value to zero out noise and / or amplify edges. algorithm, color, threshold, or window control changes are accepted at the end of a valid measurement, the current measurement in progress is not affected. software requests measurements in one of two ways: l one shot - synchronous with respect to the microcontroller. l free run - asynchronous with respect to the microcontroller. table 15: data mux registers register addr. mode bits default description dmux_chansel 0x0280 [7] 0x0 reserved r/w [6] 0x0 0: normal 1: msb/lsb byte flip r/w [5:3] 0x0 if enabled by [2] 0x0: reserved 0x1: r & g bytes are swapped 0x2: b & g bytes are swapped 0x3: r => g, g => b, b => r 0x4: r & b bytes are swapped 0x5: r => b, g => r, b => g 0x0, 0x6-0x7: reserved r/w [2] 0x0 0: normal 1: enable color swap r/w [1:0] 0x0 video source select 0x0: adc data 0x1: yuv data 0x2: dvi data 0x3: dvi xor yuv xor adc (for test only)
43/88 ade3xxx data measurement block in one-shot mode, the block indicates that measurement is valid through an auto-clear of start condition. in free-running mode, the block indicates that measurement is valid through a polling bit. in free- running mode, a freeze bit is provided to freeze the results. measurements continue with the polling bit active, but they are not updated if the freeze bit is set. 2.12.1 edge intensity the edge intensity measurement is the sum of the absolute value of the delta between adjacent pixels. a programmable threshold is applied to zero out noise and amplify edges. equation: delta_val = abs(pixela - pixelb) - threshold; delta_val = delta_val < 0 ? 0: delta_val; sum += delta_val; for all 3 color channels: sum += delta_val on red channel + delta_val on green channel + delta_val on blue channel 2.12.2 pixel sum the pixel sum is the sum of all selected pixels for either a specific color channel or all color channels within the window specified. 2.12.3 min / max the min / max reports the minimum and maximum pixel found withing the window specified. 2.12.4 pcd pixel cumulative distribution function reports the total number of pixels greater than (or less than) a programmable threshold. to switch between pixels greater than or pixel less than the threshold, a control bit is provided in the dmm_mode register when requesting a measurement. 2.12.5 h position min / max horizontal position measures the start and end of video data in inclks relative to the posedge of hsync. data horizontal start is defined as the number of inclks between posedge of hsync and the "first data pixel". first data pixel is either: l first pixel greater than the programmable threshold value, or l first pixel with the absolute value (current pixel - previous pixel) is greater than the programmable threshold value data horizontal end is defined as the number of inclks between posedge of hsync and the "last data pixel plus one". the search for the last pixels ends at the end of a window. last data pixel plus one is either: l pixel after the last pixel that is greater than the programmable threshold value,or l last pixel with the absolute value(current pixel - previous pixel) is greater than the programmable threshold value. when measurement is required, a control bit in the dmm_mode register is used to switch between the two threshold methods for first and last pixels.
data measurement block ade3xxx 44/88 the first and last pixels are measured for each line, and the earliest first and latest last for the selected pixel area are reported out at the end of the measurement. the intention is that "last data pixel plus one" minus "first data pixel" is equal to the horizontal width of the video format. 2.12.6 v position min / max vertical position measures the start and end of video data in hsyncs relative to the posedge of vsync. data vertical start is defined as the number of hsyncs between posedge of vsync and the "first data pixel line". first data pixel line definition is the first line with at least one pixel greater then the programmable threshold. data vertical end is defined as the number of hsyncs between posedge of vsync and the "first blanking line after data plus one". the first blanking line is detected and confirms that each subsequent line contains no data pixels. the confirmation of the first blanking line measurement ends at the posedge of vsync. first blanking line after data definition is the row after the last row with at least one pixel greater than the programmable threshold. the first and last data pixel lines are measured within a frame. the earliest first and latest last data pixels corresponding to the selected pixel area are reported out at the end of the measurement. the intention is that "data vertical end plus one" minus "data vertical start" is equal to the vertical height of the video format. 2.12.7 de size de size measures the number of inclks per data enable. dvi input measures precisely the input image horizontal size. at the end of the measurement (de falling edge), the measured value is compared to a programmed expected value +/- a programmed threshold. if the expected value is within the threshold, the de_size_mismatch flag is not set. if the measued size is outside the threshold, the de_size_mismatch flag is set. in free-running mode, results are updated at every line. the de_size_mismatch flag is set at de falling edge and reset at de rising edge. in one-shot mode, results are updated once and kept until they are cleared by software. the de_size_mismatch flag can only be cleared when the reset flag bit is set by software. table 16: data measurement registers (sheet 1 of 5) register name addr mode bits default description dmeas_alg_ctrl 0x0900 [7:5] reserved r/w [4] 0x0 interlace mode enable r/w [3] 0x0 0: use data valid (tv mode only) 1: use data enable for data valid r/w [2:0] 0x0 algorithm 0x0: phm edge intensity & pixel sum 0x1: dmm min / max 0x2: dmm pcd 0x3: dmm h position and v position 0x4: dmm de size 0x5 - 0x7: reserved
45/88 ade3xxx data measurement block dmeas_color_ctrl 0x0901 [7:4] reserved r/w [3:2] 0x0 color channel for dmm min / max, pcd; does not apply to h position, v position 0x0: all 0x1: red 0x2: green 0x3: blue r/w [1:0] 0x0 color channel for phm edge intensity and pixel sum algorithms 0x0: all 0x1: red 0x2: green 0x3: blue dmeas_thr_phm_edge 0x0902 r/w [7:0] 0x0 threshold value for phm edge intensity algorithm dmeas_thr_dmm 0x0903 r/w [7:0] 0x0 threshold value for dmm min / max, pcd, h position, v position dmeas_win_phm_minx_l 0x0904 r/w [7:0] 0x0 minimum x phm window [7:0] dmeas_win_phm_minx_h 0x0905 [7:4] reserved r/w [3:0] minimum x phm window [11:8] relative to hsync dmeas_win_phm_maxx_l 0x0906 r/w [7:0] 0xfff maximum x phm window [7:0] dmeas_win_phm_maxx_h 0x0907 [7:4] reserved r/w [3:0] maximum x phm window [11:8] relative to hsync, must be less than input horizontal total (llk_linelen for analog input). dmeas_win_phm_miny_l 0x0908 r/w [7:0] 0x0 minimum y phm window [7:0] dmeas_win_phm_miny_h 0x0909 [7:4] reserved r/w [3:0] minimum y phm window [11:8] relative to vsync dmeas_win_phm_maxy_l 0x090a r/w [7:0] 0xfff maximum y phm window [7:0] dmeas_win_phm_maxy_h 0x090b [7:4] reserved r/w [3:0] maximum y phm window [11:8] relative to vsync dmeas_win_dmm_minx_l 0x090c r/w [7:0] 0x0 minimum x dmm window [7:0] dmeas_win_dmm_minx_h 0x090d [7:4] 0x0 reserved r/w [3:0] minimum x dmm window [11:8] relative to hsync, does not apply for v position dmeas_win_dmm_maxx_l 0x090e r/w [7:0] 0xfff maximum x dmm window [7:0] dmeas_win_dmm_maxx_h 0x090f [7:4] 0xfff reserved r/w [3:0] maximum x dmm window [11:8] relative to hsync, does not apply for v position dmeas_win_dmm_miny_l 0x0910 r/w [7:0] 0x0 minimum y dmm window [7:0] table 16: data measurement registers (sheet 2 of 5) register name addr mode bits default description
data measurement block ade3xxx 46/88 dmeas_win_dmm_miny_h 0x0911 [7:4] reserved r/w [3:0] minimum y dmm window [11:8] relative to vsync dmeas_win_dmm_maxy_l 0x0912 r/w [7:0] 0xfff maximum y dmm window [7:0] dmeas_win_dmm_maxy_h 0x0913 [7:4] reserved r/w [3:0] maximum y dmm window [11:8] relative to vsync dmeas_phm_edgesel 0x0914 [7:2] 0xfff reserved r/w [1] 0x0 vsync edge select for phm measurements 0: rising edge 1: falling edge r/w [0] 0x0 hsync edge select for phm measurements 0: rising edge 1: falling edge dmeas_dmm_edgesel 0x0915 [7:2] reserved r/w [1] 0x0 vsync edge select for dmm measurements 0: rising edge 1: falling edge r/w [0] 0x0 hsync edge select for dmm measurements 0: rising edge 1: falling edge dmeas_phm_mode_ctrl 0x0916 [7:5] reserved r/w [4] 0x0 clear phm result registers r/w [3] 0x0 0: do not freeze the results in free-running mode. new result will be available on the next and subsequent toggle of the polling bit. 1: freeze the current results in free-running mode. the polling bit will still toggle and the block continues to free run; however, results will not update. no meaning in one-shot mode. r/w [2] 0x0 phm measurement polling bit. toggles at the end of each measurement in free-run mode. undefined in one-shot mode. r/w [1] 0x0 phm algorithm measurement start. in free-run mode it enables measurements. in one-shot mode it triggers the start of a measurement and is reset to zero when the measurement is complete. r/w [0] 0x0 0: phm free-run mode. 1: phm one-shot mode. table 16: data measurement registers (sheet 3 of 5) register name addr mode bits default description
47/88 ade3xxx data measurement block dmeas_dmm_mode_ctrl 0x0917 r/w [7] 0x0 listen to odd frame only. applies only if the odd signal is present from yuv. the results in the vertical position algorithm are updated with only the odd frame if this bit is set. r/w [6] 0x0 pcd algorithm 0: pixel < threshold 1: pixel >= threshold r/w [5] 0x0 horizontal position algorithm 0: pixel > threshold 1: abs (pixel - previous pixel) > threshold r/w [4] 0x0 clear dmm result registers r/w [3] 0x0 0: do not freeze the results in free-running mode. new result will be available on the next and subsequent toggle of the polling bit. 1: freeze the current results in free-running mode. the polling bit will still toggle and the block continues to free run; however, results will not update. no meaning in one-shot mode. r/w [2] 0x0 dmm measurement polling bit. toggles at the end of each measurement in free-run mode. undefined in one-shot mode. r/w [1] 0x0 dmm algorithm measurement start. in free-run mode it enables measurements. in one-shot mode it triggers the start of a measurement and is reset to zero when the measurement is complete. r/w [0] 0x0 0: dmm free-running mode. 1: dmm one-shot mode. dmeas_dmm_de_ref_l 0x0918 r/w [7:0] 0x0 de size expected result dmeas_dmm_de_ref_h 0x0919 r/w [7:0] dmeas_dmm_de_tol 0x091a r/w [7:0] 0x0 de size tolerance threshold value dmeas_dmm_de_rst 0x091b [7:1] reserved r/w [0] 0x0 reset the dmm flag in one-shot mode dmeas_data_phm_edge0 0x091c r [7:0] result of phm edge intensity algorithm dmeas_data_phm_edge1 0x091d r [7:0] dmeas_data_phm_edge2 0x091e r [7:0] dmeas_data_phm_edge3 0x091f r [7:0] dmeas_data_phm_psum0 0x0920 r [7:0] result for phm pixel sum algorithm dmeas_data_phm_psum1 0x0921 r [7:0] dmeas_data_phm_psum2 0x0922 r [7:0] dmeas_data_phm_psum3 0x0923 r [7:0] dmeas_data_dmm_min 0x0924 r [7:0] result for dmm minimum pixel value found. dmeas_data_dmm_max 0x0925 r [7:0] result for dmm maxmum pixel value found. table 16: data measurement registers (sheet 4 of 5) register name addr mode bits default description
programmable nonlinearity block ade3xxx 48/88 2.13 programmable nonlinearity block the programmable nonlinearity (pnl) block performs a gamma type enhancement to all color channels prior to the scaler to suppress halo and roping effects. for best performance, tune the dmeas_data_dmm_pcd_l 0x0926 r [7:0] result for dmm pixel cumulative distribution dmeas_data_dmm_pcd_m 0x0927 r [7:0] dmeas_data_dmm_pcd_h 0x0928 r [7:0] dmeas_data_dmm_hposmin_l 0x0929 r [7:0] dmm hposition of first pixel [7:0] dmeas_data_dmm_hposmin_h 0x092a [7:4] reserved r [3:0] dmm hposition of first pixel [11:8] dmeas_data_dmm_hposmax_l 0x092b r [7:0] dmm hposition of last pixel [7:0] dmeas_data_dmm_hposmax_h 0x092c [7:4] reserved r [3:0] dmm hposition of last pixel [11:8] dmeas_data_dmm_vposmin_l 0x092d r [7:0] dmm vposition of first line [7:0] dmeas_data_dmm_vposmin_h 0x092e [7:4] reserved r [3:0] dmm vposition of first line [11:8] dmeas_data_dmm_vposmax_l 0x092f r [7:0] dmm vposition of last line [7:0] dmeas_data_dmm_vposmax_h 0x0930 [7:4] reserved r [3:0] dmm vposition of last line [11:8] dmeas_data_dmm_size_l 0x0931 r [7:0] number of inclks per de = input horizontal pixel size for dvi mode selection. dmeas_data_dmm_size_h 0x0932 r [7:0] dmeas_data_dmm_de_status 0x0933 [7:1] reserved r [0] de measured value does not match expected value within the de tolerance dmeas_scr_pad_0 0x0934 r [7:0] 0x0 scratch pad registers dmeas_scr_pad_1 0x0935 r/w [7:0] dmeas_scr_pad_2 0x0936 r/w [7:0] dmeas_scr_pad_3 0x0937 r/w [7:0] dmeas_scr_pad_4 0x0938 r/w [7:0] dmeas_scr_pad_5 0x0939 r/w [7:0] dmeas_scr_pad_6 0x093a r/w [7:0] dmeas_scr_pad_7 0x093b r/w [7:0] dmeas_scr_pad_8 0x093c r/w [7:0] dmeas_scr_pad_9 0x093d r/w [7:0] dmeas_scr_pad_10 0x093e r/w [7:0] dmeas_scr_pad_11 0x093f r/w [7:0] dmeas_scr_pad_12 0x0940 r/w [7:0] dmeas_scr_pad_13 0x0941 r/w [7:0] dmeas_scr_pad_14 0x0942 r/w [7:0] dmeas_scr_pad_15 0x0943 r/w [7:0] table 16: data measurement registers (sheet 5 of 5) register name addr mode bits default description
49/88 ade3xxx scaler block pnl block to the lcd gamma value, then the post-scaler gamma ram implements the corresponding inverse gamma function. 2.14 scaler block the scale module resizes images from one resolution to another. for this, a 3x3 non-separable scaling filter performs a dot product of the input pixel values with a weighting vector computed from the chosen filtering function. to sharpen text without introducing excessive artifacts, the output pixel contrast level is adjusted with the context value measured over a 3x3 grid in the relevant area of the source image. for proper scaler operation, set the sclk frequency to be greater than the max of dclk and in_hpixel x dclk_freq / (dest_hpixel x pixel_avg). table 17: pnl registers register name addr mode bits default description pnl_ctrl 0x0080 r/w [7:6] 0x0 reserved [5:0] 0x0 0x00: bypass 0x01 - 0x1f: gamma <1.0 0x20 - 0x3f: gamma >1.0 0x30: gamma = 2.2 table 18: scaler block registers (sheet 1 of 3) register name addr mode bits default description scl_src_hpix_l 0x0a00 r/w [7:0] 0x0 input horizontal resolution in top 12 bits bits [3:0] must be set to zero. if pixel averaging is necessary then this register contains the averaged, round-down resolution, e.g, if the original resolution is 65 and if the mode is averaging-by-2 then 32 should be programmed in this register. scl_src_hpix_h 0x0a01 r/w [7:0] scl_src_vpix_l 0x0a02 r/w [7:0] 0x0 input vertical resolution [3:0] must be set to 0. scl_src_vpix_h 0x0a03 r/w [7:0] scl_des_hpix_l 0x0a04 r/w [7:0] 0x0 scaled active area width in pixels [15:4] = integer; [3:0] = fraction scl_des_hpix_h 0x0a05 r/w [7:0] scl_des_vpix_l 0x0a08 r/w [7:0] 0x0 scaled active area height in lines [15:4] = integer; [3:0] = fraction scl_des_vpix_h 0x0a09 r/w [7:0] scl_hpos_l 0x0a0a r/w [7:0] 0x0 horizontal position of upper left pixel of active output data [15:4] = integer; [3:0] = fraction scl_hpos_h 0x0a0b r/w [7:0] scl_vpos_e_l 0x0a0e r/w [7:0] 0x0 vertical position of upper left pixel of output data for even/non-interlace frames [15:4] = integer; [3:0] = fraction scl_vpos_e_h 0x0a0f r/w [7:0] scl_vpos_o_l 0x0a10 r/w [7:0] 0x0 vertical position of the upper left pixel of output data of odd fields bits [15:4] = integer; bits [3:0] = fraction scl_vpos_o_h 0x0a11 r/w [7:0] scl_thres_slope 0x0a12 r/w [7:6] 0x0 reserved [5:0] 0x28 slope of the contrast amplification function
scaler block ade3xxx 50/88 scl_thres_offset_l 0x0a13 r/w [7:0] 0x40 offset of the contrast amplification function [7:0] scl_thres_offset_h 0x0a14 r/w [7:2] 0x0 reserved r/w [1:0] 0x2 offset of the contrast amplification function [9:8] scl_cbbypass 0x0a15 r/w [7:2] 0x0 reserved r/w [1] 0x0 0: normal 1: tcon control of contrast amplification r/w [0] 0x0 0: contrast amplification enabled 1: bypass contrast amplification scl_con_cal_sel 0x0a16 [7:1] reserved r/w [0] 0x0 0: context = max of rgb pk-pk 1: context = sum of rgb pk-pk scl_testcon 0x0a17 [7:2] 6b contrast amplification test data r/w [1:0] 0x0 0x0, 0x3: normal 0x1: force input data into the contrast amplifiation function to bits [7:2] 0x2: force the output context data to be bits [5:2] scl_lut1 0x0a18 r/w [7:0] 0xfa sigmoidal function lut entry 1, 8b 2s complement scl_lut2 0x0a19 r/w [7:0] 0xf7 sigmoidal function lut entry 2, 8b 2s complement scl_lut3 0x0a1a r/w [7:0] 0xf7 sigmoidal function lut entry 3, 8b 2s complement scl_lut4 0x0a1b r/w [7:0] 0xfc sigmoidal function lut entry 4, 8b 2s complement scl_lut5 0x0a1c r/w [7:0] 0x2 sigmoidal function lut entry 5, 8b 2s complement scl_lut6 0x0a1d r/w [7:0] 0x0d sigmoidal function lut entry 6, 8b 2s complement scl_lut7 0x0a1e r/w [7:0] 0x17 sigmoidal function lut entry 7, 8b 2s complement scl_lut8 0x0a1f r/w [7:0] 0x21 sigmoidal function lut entry 8, 8b 2s complement scl_lut9 0x0a20 r/w [7:0] 0x28 sigmoidal function lut entry 9, 8b 2s complement scl_lut10 0x0a21 r/w [7:0] 0x2c sigmoidal function lut entry 10, 8b 2s complement scl_lut11 0x0a22 r/w [7:0] 0x2c sigmoidal function lut entry 11, 8b 2s complement scl_lut12 0x0a23 r/w [7:0] 0x28 sigmoidal function lut entry 12, 8b 2s complement scl_lut13 0x0a24 r/w [7:0] 0x21 sigmoidal function lut entry 13, 8b 2s complement scl_lut14 0x0a25 r/w [7:0] 0x17 sigmoidal function lut entry 14, 8b 2s complement table 18: scaler block registers (sheet 2 of 3) register name addr mode bits default description
51/88 ade3xxx scaler block scl_lut15 0x0a26 r/w [7:0] 0x0c sigmoidal function lut entry 15, 8b 2s complement scl_bgcolor_r 0x0a27 r/w [7:0] 0x0 red component of background color scl_bgcolor_g 0x0a28 r/w [7:0] 0x0 green component of background color scl_bgcolor_b 0x0a29 r/w [7:0] 0x0 blue component of background color scl_bcolor_ctrl 0x0a2a r/w [7] 0x0 0: normal 1: force image to background color r/w [6] 0x0 top & botton border control 0: pixel replicating 1: background color blending r/w [5] 0x0 left & right border control: 0: pixel replicating 1: background color blending r/w [4] 0x0 force output data as described in bit [1] when the maximum output vertical is reached. r/w [3] 0x0 force output data as described in bit [1] when an abnormal codition is detected by the sync measurement module. r/w [2] 0x0 when the scaler is not running, force the ouput data to black if this bit is 0 or to the background color if the bit is 1. r/w [1] 0x0 if an abnormality is detected in the sync measurement module or if the maximum output vertical total has been reached, force the ouput data to black if this bit is 0 or to white if this bit is 1. r/w [0] 0x0 during blanking, force output data to black if this bit is 0 or to the background color if this bit is 1. scl_average_ik 0x0af0 [7:3] reserved r/w [2:1] 0x0 0x0: bypass 0x1: horizontal average by 2 0x2: horizontal average by 4 0x3: horizontal average by 8 r/w [0] 0x0 0: no pixel average 1: enable pixel averager this function is only necessary if the input horizontal resolution is greater than 1280 pixels. scl_flip_h_ik 0x0af1 [7:1] reserved r/w [0] 0x0 horizontal flip enable table 18: scaler block registers (sheet 3 of 3) register name addr mode bits default description
output sequencer block ade3xxx 52/88 2.15 output sequencer block the output sequencer module provides timing for the output video interface. it allows sufficient flexibility to support a broad range of smart panel applications as well. the timing unit is based on horizontal and vertical counters, which are locked with the input video stream. frame synchronization due to the limited pixel memory of the chip, the output active video needs to be perfectly synchronized with the input active video. this mode of operation is called frame lock . timing unit the timing unit consists of a 12-bit horizontal and a 12-bit vertical counter, synchronized with the input video stream. signal generation the signal generation unit generates all fixed control signals like hsync, vsync and data enable as well as those required to run the internal data path. also included, a generalized timing section supports flat panel tcon signals like polarity and other control signals. figure 4: output sequencer block diagram figure 5: frame lock operation
53/88 ade3xxx output sequencer block table 19: output sequencer registers (sheet 1 of 2) register name addr mode bits default description osq_control 0x0bc1 r [7] out_vmax detected, sticky bit r/w [6] 0x0 out_vmax detect reset r/w [5] 0x0 interlace enable r/w [4] 0x0 fractional line extend 0: +1 1: +2 r/w [3] 0x0 frame lock reference 0: last input pixel 1: first input pixel r/w [2] 0x0 frame lock selection 0: last line variable 1: fixed line length r [1] shutdown ready - current frame has completed, panel can now be shut down r/w [0] 0x0 run sequencer when 1, otherwise stop at the end of the frame and set shutdown ready flag (bit [1]) osq_clock_frac 0x0bc2 r/w [7:0] 0x0 the fraction of lines (/256) that are extended osq_out_htotal_l 0x0bc3 r/w [7:0] 0x0 nominal output horizontal total [7:0] osq_out_htotal_h 0x0bc4 [7:4] reserved r/w [3:0] 0x0 nominal output horizontal total [11:8] osq_out_vtotal_min_l 0x0bc5 r/w [7:0] 0x0 minimum output vertical total, used to rearm for vert_enab trigger [7:0] osq_out_vtotal_min_h 0x0bc6 [7:4] reserved r/w [3:0] 0x0 minimum output vertical total, used to rearm for vert_enab triggers [11:8] osq_vtotal_max_l 0x0bc7 r/w [7:0] 0x0 maximum output vertical total, prevents panel burn with loss of vert_enab trigger [7:0] osq_vtotal_max_h 0x0bc8 [7:4] reserved r/w [3:0] 0x0 maximum output vertical total, prevents panel burn with loss of vert_enab triggers [11:8] osq_verten_dly_e_l 0x0bc9 r/w [7:0] 0x0 delay of the vert_enab signal to the reset of the horizontal and vertical counters, even and non- interlaced modes [15:0] osq_verten_dly_e_m 0x0bca r/w [7:0] 0x0 osq_verten_dly_e_h 0x0bcb [7:4] reserved r/w [3:0] 0x0 delay of the vert_enab signal to the reset of the horizontal and vertical counters, even and non- interlaced [19:16] osq_verten_dly_o_l 0x0bcc r/w [7:0] 0x0 delay of the vert_enab signal to the reset of the horizontal and vertical counters, odd frame in interlace mode only [15:0] osq_verten_dly_o_m 0x0bcd r/w [7:0] 0x0
output sequencer block ade3xxx 54/88 osq_verten_dly_o_h 0x0bce [7:4] 0x0 reserved r/w [3:0] 0x0 delay of the vert_enab signal to the reset of the horizontal and vertical counters, odd frame in interlace mode only [19:16] osq_vsync_set_l 0x0bcf r/w [7:0] 0x0 vertical count at which vsync goes high [7:0] osq_vsync_set_h 0x0bd0 [7:4] 0x0 reserved r/w [3:0] 0x0 vertical count at which vsync goes high [11:8] osq_vsync_rst_l 0x0bd1 r/w [7:0] 0x0 vertical count at which vsync goes low [7:0] osq_vsync_rst_h 0x0bd2 [7:4] 0x0 reserved r/w [3:0] 0x0 vertical count at which vsync goes low [11:8] osq_hsync_set_l 0x0bd3 r/w [7:0] 0x0 horizontal count at which hsync goes high [7:0] osq_hsync_set_h 0x0bd4 [7:4] 0x0 reserved r/w [3:0] 0x0 horizontal count at which hsync goes high [11:8] osq_hsync_rst_l 0x0bd5 r/w [7:0] 0x0 horizontal count at which hsync goes low [7:0] osq_hsync_rst_h 0x0bd6 [7:4] 0x0 reserved r/w [3:0] 0x0 horizontal count at which hsync goes low [11:8] osq_henab_set_l 0x0bd7 r/w [7:0] 0x0 horizontal count at which enab goes high [7:0] osq_henab_set_h 0x0bd8 [7:4] reserved r/w [3:0] horizontal count at which enab goes high [11:8] value must be greater than 0x01c osq_henab_rst_l 0x0bd9 r/w [7:0] 0x0 horizontal count at which enab goes low [7:0] osq_henab_rst_h 0x0bda [7:4] reserved r/w [3:0] horizontal count at which enab goes low [11:8] osq_venab_set_l 0x0bdb r/w [7:0] 0x0 vertical count at which enab goes high [7:0] osq_venab_set_h 0x0bdc [7:4] 0x0 reserved r/w [3:0] 0x0 vertical count at which enab goes high [11:8] osq_venab_rst_l 0x0bdd r/w [7:0] 0x0 vertical count at which enab goes low [7:0] osq_venab_rst_h 0x0bde [7:4] 0x0 reserved r/w [3:0] 0x0 vertical count at which enab goes low [11:8] osq_out_vcount 0x0bdf r [7:0] 0x0 vertical counter /16 indicating the current frame position table 19: output sequencer registers (sheet 2 of 2) register name addr mode bits default description
55/88 ade3xxx timing controller (tcon) block 2.16 timing controller (tcon) block the output timing controller module provides timing for smart panel applications. the timing unit is based on horizontal and vertical counters locked with the output video stream. a set of programmable comparators provides all necessary time events to generate signals for the driver interface. please refer to the programming tools for more details. figure 6: tcon block diagram table 20: tcon registers (sheet 1 of 6) register name addr. mode bits default description tcon_control 0x0bc0 [7:3] reserved r/w [2] 0 0: no tcon pipe delay matching 1: tcon pipe delay enabled (normal) r/w [1] 0 initialize srtds r/w [0] 0 enabletcon tcon_comp_0_l 0x0b10 r/w [7:0] 0 count comparison value [7:0] tcon_comp_0_h 0x0b11 r/w [7:5] reserved r/w [4] 0: horizontal count compare 1: vertical count compare r/w [3:0] count comparison value [11:8] tcon_comp_1_l 0x0b12 r/w [7:0] 0 refer to tcon_comp_0 for definition tcon_comp_1_h 0x0b13 r/w [7:0] tcon_comp_2_l 0x0b14 r/w [7:0] 0 refer to tcon_comp_0 for definition tcon_comp_2_h 0x0b15 r/w [7:0] tcon_comp_3_l 0x0b16 r/w [7:0] 0 refer to tcon_comp_0 for definition tcon_comp_3_h 0x0b17 r/w [7:0] tcon_comp_4_l 0x0b18 r/w [7:0] 0 refer to tcon_comp_0 for definition tcon_comp_4_h 0x0b19 r/w [7:0] tcon_comp_5_l 0x0b1a r/w [7:0] 0 refer to tcon_comp_0 for definition tcon_comp_5_h 0x0b1b r/w [7:0] tcon_comp_6_l 0x0b1c r/w [7:0] 0 refer to tcon_comp_0 for definition tcon_comp_6_h 0x0b1d r/w [7:0]
timing controller (tcon) block ade3xxx 56/88 tcon_comp_7_l 0x0b1e r/w [7:0] 0 refer to tcon_comp_0 for definition tcon_comp_7_h 0x0b1f r/w [7:0] tcon_comp_8_l 0x0b20 r/w [7:0] 0 refer to tcon_comp_0 for definition tcon_comp_8_h 0x0b21 r/w [7:0] tcon_comp_9_l 0x0b22 r/w [7:0] 0 refer to tcon_comp_0 for definition tcon_comp_9_h 0x0b23 r/w [7:0] tcon_comp_10_l 0x0b24 r/w [7:0] 0 refer to tcon_comp_0 for definition tcon_comp_10_h 0x0b25 r/w [7:0] tcon_comp_11_l 0x0b26 r/w [7:0] 0 refer to tcon_comp_0 for definition tcon_comp_11_h 0x0b27 r/w [7:0] tcon_comp_12_l 0x0b28 r/w [7:0] 0 refer to tcon_comp_0 for definition tcon_comp_12_h 0x0b29 r/w [7:0] tcon_comp_13_l 0x0b2a r/w [7:0] 0 refer to tcon_comp_0 for definition tcon_comp_13_h 0x0b2b r/w [7:0] tcon_comp_14_l 0x0b2c r/w [7:0] 0 refer to tcon_comp_0 for definition tcon_comp_14_h 0x0b2d r/w [7:0] tcon_comp_15_l v0b2e r/w [7:0] 0 refer to tcon_comp_0 for definition tcon_comp_15_h v0b2f r/w [7:0] tcon_comp_16_l 0x0b30 r/w [7:0] 0 refer to tcon_comp_0 for definition tcon_comp_16_h 0x0b31 r/w [7:0] tcon_comp_17_l 0x0b32 r/w [7:0] 0x0 refer to tcon_comp_0 for definition tcon_comp_17_h 0x0b33 r/w [7:0] tcon_comp_18_l 0x0b34 r/w [7:0] 0x0 refer to tcon_comp_0 for definition tcon_comp_18_h 0x0b35 r/w [7:0] tcon_comp_19_l 0x0b36 r/w [7:0] 0x0 refer to tcon_comp_0 for definition tcon_comp_19_h 0x0b37 r/w [7:0] tcon_comp_20_l 0x0b38 r/w [7:0] 0x0 refer to tcon_comp_0 for definition tcon_comp_20_h 0x0b39 r/w [7:0] tcon_comp_21_l 0x0b3a r/w [7:0] 0x0 refer to tcon_comp_0 for definition tcon_comp_21_h 0x0b3b r/w [7:0] tcon_comp_22_l 0x0b3c r/w [7:0] 0x0 refer to tcon_comp_0 for definition tcon_comp_22_h 0x0b3d r/w [7:0] tcon_comp_23_l 0x0b3e r/w [7:0] 0x0 refer to tcon_comp_0 for definition tcon_comp_23_h 0x0b3f r/w [7:0] tcon_comp_24_l 0x0b40 r/w [7:0] 0x0 refer to tcon_comp_0 for definition tcon_comp_24_h 0x0b41 r/w [7:0] tcon_comp_25_l 0x0b42 r/w [7:0] 0x0 refer to tcon_comp_0 for definition tcon_comp_25_h 0x0b43 r/w [7:0] table 20: tcon registers (sheet 2 of 6) register name addr. mode bits default description
57/88 ade3xxx timing controller (tcon) block tcon_comp_26_l 0x0b44 r/w [7:0] 0x0 refer to tcon_comp_0 for definition tcon_comp_26_h 0x0b45 r/w [7:0] tcon_comp_27_l 0x0b46 r/w [7:0] 0x0 refer to tcon_comp_0 for definition tcon_comp_27_h 0x0b47 r/w [7:0] tcon_srtd_0 0x0b50 [7:4] reserved r/w [3] 0x0 srtd initialization state r/w [2:0] 0x0 0x0: f (a&b,&c&d,0,0) 0x1: f (a&b,&c&d,0,0) 0x2: f (a&b,&c&d,0,0) 0x3: f (0,0,a&b,0) 0x4: f (0,0,0,a&b) 0x5: f (0,0,0,a|b) 0x6: f (0,0,0,a^b) 0x7: f (0,0,0,!(a&b)) where f(set, reset, toggle, dflop) is a configurable logic/flop element tcon_srtd_1 0x0b51 r/w [7:0] refer to tcon_srtd_0 for definition tcon_srtd_2 0x0b52 r/w [7:0] refer to tcon_srtd_0 for definition tcon_srtd_3 0x0b53 r/w [7:0] refer to tcon_srtd_0 for definition tcon_srtd_4 0x0b54 r/w [7:0] refer to tcon_srtd_0 for definition tcon_srtd_5 0x0b55 r/w [7:0] refer to tcon_srtd_0 for definition tcon_srtd_6 0x0b56 r/w [7:0] refer to tcon_srtd_0 for definition tcon_srtd_7 0x0b57 r/w [7:0] refer to tcon_srtd_0 for definition tcon_srtd_8 0x0b58 r/w [7:0] refer to tcon_srtd_0 for definition tcon_srtd_9 0x0b59 r/w [7:0] refer to tcon_srtd_0 for definition tcon_srtd_10 0x0b5a r/w [7:0] refer to tcon_srtd_0 for definition tcon_srtd_11 0x0b5b r/w [7:0] refer to tcon_srtd_0 for definition tcon_srtd_12 0x0b5c r/w [7:0] refer to tcon_srtd_0 for definition tcon_srtd_13 0x0b5d r/w [7:0] refer to tcon_srtd_0 for definition tcon_srtd_14 0x0b5e r/w [7:0] refer to tcon_srtd_0 for definition tcon_srtd_15 0x0b5f r/w [7:0] refer to tcon_srtd_0 for definition tcon_srtd_16 0x0b60 r/w [7:0] refer to tcon_srtd_0 for definition tcon_srtd_17 0x0b61 r/w [7:0] refer to tcon_srtd_0 for definition tcon_srtd_18 0x0b62 r/w [7:0] refer to tcon_srtd_0 for definition tcon_srtd_19 0x0b63 r/w [7:0] refer to tcon_srtd_0 for definition tcon_srtd_20 0x0b64 r/w [7:0] refer to tcon_srtd_0 for definition tcon_srtd_21 0x0b65 r/w [7:0] refer to tcon_srtd_0 for definition tcon_srtd_22 0x0b66 r/w [7:0] refer to tcon_srtd_0 for definition tcon_srtd_23 0x0b67 r/w [7:0] refer to tcon_srtd_0 for definition tcon_srtd_24 0x0b68 r/w [7:0] refer to tcon_srtd_0 for definition tcon_srtd_25 0x0b69 r/w [7:0] refer to tcon_srtd_0 for definition tcon_srtd_26 0x0b6a r/w [7:0] refer to tcon_srtd_0 for definition table 20: tcon registers (sheet 3 of 6) register name addr. mode bits default description
timing controller (tcon) block ade3xxx 58/88 tcon_srtd_27 0x0b6b r/w [7:0] refer to tcon_srtd_0 for definition tcon_srtd_28 0x0b6c r/w [7:0] refer to tcon_srtd_0 for definition tcon_srtd_29 0x0b6d r/w [7:0] refer to tcon_srtd_0 for definition tcon_srtd_30 0x0b6e r/w [7:0] refer to tcon_srtd_0 for definition tcon_srtd_31 0x0b6f r/w [7:0] refer to tcon_srtd_0 for definition tcon_x_0 0x0b80 [7:6] reserved r/w [5:0] 0x0 input selection for srtd_0.a 0x00: 0 0x01: 1 0x02: external tcon input pin 0x03: i2c srtd init bit 0x04 - 0x1f: comp0 - comp27 0x20 - 0x37: srtd8 - srtd31 0x38: 2 frame + 1 line + 2 pixel toggle 0x39: 2 frame + 2 line + 1 pixel toggle 0x3a: hcount[0] 0x3b: hcount[1] 0x3c: hcount[0] 0x3d: hcount[1] 0x3e: fcount[0] 0x3f: fcount[1] tcon_x_1 0x0b81 r/w [7:0] input selection for srtd_0.b 1 tcon_x_2 0x0b82 r/w [7:0] input selection for srtd_1.a 1 tcon_x_3 0x0b83 r/w [7:0] input selection for srtd_1.b 1 tcon_x_4 0x0b84 r/w [7:0] input selection for srtd_2.a 1 tcon_x_5 0x0b85 r/w [7:0] input selection for srtd_2.b 1 tcon_x_6 0x0b86 r/w [7:0] input selection for srtd_3.a 1 tcon_x_7 0x0b87 r/w [7:0] input selection for srtd_3.b 1 tcon_x_8 0x0b88 r/w [7:0] input selection for srtd_4.a 1 tcon_x_9 0x0b89 r/w [7:0] input selection for srtd_4.b 1 tcon_x_10 0x0b8a r/w [7:0] input selection for srtd_5.a 1 tcon_x_11 0x0b8b r/w [7:0] input selection for srtd_5.b 1 tcon_x_12 0x0b8c r/w [7:0] input selection for srtd_6.a 1 tcon_x_13 0x0b8d r/w [7:0] input selection for srtd_6.b 1 tcon_x_14 0x0b8e r/w [7:0] input selection for srtd_7. 1 tcon_x_15 0x0b8f r/w [7:0] input selection for srtd_7.b 1 tcon_x_16 0x0b90 r/w [7:0] input selection for srtd_8. 1 tcon_x_17 0x0b91 r/w [7:0] input selection for srtd_8.b 1 tcon_x_18 0x0b92 r/w [7:0] input selection for srtd_9.a 1 tcon_x_19 0x0b93 r/w [7:0] input selection for srtd_9.b 1 tcon_x_20 0x0b94 r/w [7:0] input selection for srtd_10.a 1 table 20: tcon registers (sheet 4 of 6) register name addr. mode bits default description
59/88 ade3xxx timing controller (tcon) block tcon_x_21 0x0b95 r/w [7:0] input selection for srtd_10.b 1 tcon_x_22 0x0b96 r/w [7:0] input selection for srtd_11.a 1 tcon_x_23 0x0b97 r/w [7:0] input selection for srtd_11.b 1 tcon_x_24 0x0b98 r/w [7:0] input selection for srtd_12.a 1 tcon_x_25 0x0b99 r/w [7:0] input selection for srtd_12.b 1 tcon_x_26 0x0b9a r/w [7:0] input selection for srtd_13.a 1 tcon_x_27 0x0b9b r/w [7:0] input selection for srtd_13.b 1 tcon_x_28 0x0b9c r/w [7:0] input selection for srtd_14.a 1 tcon_x_29 0x0b9d r/w [7:0] input selection for srtd_14.b 1 tcon_x_30 0x0b9e r/w [7:0] input selection for srtd_15.a 1 tcon_x_31 0x0b9f r/w [7:0] input selection for srtd_15.b 1 tcon_x_32 0x0ba0 r/w [7:0] input selection for srtd_16.a 1 tcon_x_33 0x0ba1 r/w [7:0] input selection for srtd_16.b 1 tcon_x_34 0x0ba2 r/w [7:0] input selection for srtd_17.a 1 tcon_x_35 0x0ba3 r/w [7:0] input selection for srtd_17.b 1 tcon_x_36 0x0ba4 r/w [7:0] input selection for srtd_18.a 1 tcon_x_37 0x0ba5 r/w [7:0] input selection for srtd_18.b 1 tcon_x_38 0x0ba6 r/w [7:0] input selection for srtd_19.a 1 tcon_x_39 0x0ba7 r/w [7:0] input selection for srtd_19.b 1 tcon_x_40 0x0ba8 r/w [7:0] input selection for srtd_20.a 1 tcon_x_41 0x0ba9 r/w [7:0] input selection for srtd_20.b 1 tcon_x_42 0x0baa r/w [7:0] input selection for srtd_21.a 1 tcon_x_43 0x0bab r/w [7:0] input selection for srtd_21.b 1 tcon_x_44 0x0bac r/w [7:0] input selection for srtd_22.a 1 tcon_x_45 0x0bad r/w [7:0] input selection for srtd_22.b 1 tcon_x_46 0x0bae r/w [7:0] input selection for srtd_23.a 1 tcon_x_47 0x0baf r/w [7:0] input selection for srtd_23.b 1 tcon_x_48 0x0bb0 r/w [7:0] input selection for srtd_24.a 1 tcon_x_49 0x0bb1 r/w [7:0] input selection for srtd_24.b 1 tcon_x_50 0x0bb2 r/w [7:0] input selection for srtd_25.a 1 tcon_x_51 0x0bb3 r/w [7:0] input selection for srtd_25.b 1 tcon_x_52 0x0bb4 r/w [7:0] input selection for srtd_26.a 1 tcon_x_53 0x0bb5 r/w [7:0] input selection for srtd_26.b 1 tcon_x_54 0x0bb6 r/w [7:0] input selection for srtd_27.a 1 table 20: tcon registers (sheet 5 of 6) register name addr. mode bits default description
pattern generator block ade3xxx 60/88 2.17 pattern generator block the integrated pattern generator displays a set of graphic patterns to help debugging systems and test lcd panels. it is located ahead of the color management blo ck, all generated colors are subject to further transforms. the screen can be split into a programmable grid of up to 8x8 areas. one of two independent programmable patterns are displayed in each area. screen split a set of eight grid registers grid0 - grid7, each with 8 bits, represents a block map of the grid (8x8 blocks). each bit from the grid registers represents one rectangular (gridx)x(gridy) block of pixels which covers the lcd screen display area. within these registers, a 0 selects pattern 0 (defined below) and a 1 selects pattern 1. all cells are the same size, defined by one horizontal and one vertical grid block size registers gridx and gridy . tcon_x_55 0x0bb7 r/w [7:0] input selection for srtd_27.b 1 tcon_x_56 0x0bb8 r/w [7:0] input selection for srtd_28.a 1 tcon_x_57 0x0bb9 r/w [7:0] input selection for srtd_28.b 1 tcon_x_58 0x0bba r/w [7:0] input selection for srtd_29.a 1 tcon_x_59 0x0bbb r/w [7:0] input selection for srtd_29.b 1 tcon_x_60 0x0bbc r/w [7:0] input selection for srtd_30.a 1 tcon_x_61 0x0bbd r/w [7:0] input selection for srtd_30.b 1 tcon_x_62 0x0bbe r/w [7:0] input selection for srtd_31.a 1 tcon_x_63 0x0bbf r/w [7:0] input selection for srtd_31.b 1 1. refer to register tcon_x_o for definition. figure 7: pattern generator: screen split table 20: tcon registers (sheet 6 of 6) register name addr. mode bits default description
61/88 ade3xxx pattern generator block when the programmed block size corresponds to a larger 8x8 grid than the total screen area, only the blocks or part of blocks included in the output screen space are rendered. the 8x8 block set is upper left justified. all blocks from the right and bottom sides which are outside the total display area are not rendered. when the programmed block size corresponds to a smaller 8x8 grid than the total screen area, the part of the screen area which is outside the 8x8 grid is forced to black. pattern engine the pattern generator has two pattern display engines to display two patterns simultaneously on the lcd screen. each engine displays horizontal or vertical bicolor stripes, bicolor checkers, color bars, gray scales or color scales. it is also possible to select the video stream from the scaler as a pattern. the pattern engine displays a bi-directional x-y symmetric pattern. two 24b co lors, c0 and c1, are alternately displayed with a horizontal period of width and vertical period of height. programming a large width and a small height generates horizontal bars whereas the opposite generates vertical bars. programming small numbers for width and height generates checker patterns. both patterns are also given x and y offset attributes, they can be centered inside the grid blo cks. a gradient effect can be applied independently on each pattern, to either or both horizontal and vertical directions. the gradient effect takes two parameters: step and delta that define a ramp. borders the border generator adds a single pixel width border to the whole display area. each side color of the display is selectable among 8 independent colors. table 21: pgen registers (sheet 1 of 4) register name addr mode bits default description pgen_pgen_enab 0x0600 [7:1] reserved r/w [0] 0x0 0 = disable pgen block 1 = enable pgen block pgen_grid0 0x0601 r/w [7:0] 0x0 grid row 0 pgen_grid1 0x0602 r/w [7:0] 0x0 grid row 1 pgen_grid2 0x0603 r/w [7:0] 0x0 grid row 2 pgen_grid3 0x0604 r/w [7:0] 0x0 grid row 3 pgen_grid4 0x0605 r/w [7:0] 0x0 grid row 4 pgen_grid5 0x0606 r/w [7:0] 0x0 grid row 5 pgen_grid6 0x0607 r/w [7:0] 0x0 grid row 6 pgen_grid7 0x0608 r/w [7:0] 0x0 grid row 7 pgen_grid_x_l 0x0609 r/w [7:0] 0x0 width of a grid block in pixels [7:0] pgen_grid_x_h 0x060a [7:4] reserved r/w [3:0] 0x0 width of a grid block in pixels [11:8] pgen_grid_y_l 0x060b r/w [7:0] 0x0 height of a grid block in pixels [7:0] pgen_grid_y_h 0x060c [7:4] reserved r/w [3:0] 0x0 height of a grid block in pixels [11:8] pgen_grid_x_offset_x_l 0x060d r/w [7:0] 0x0 grid block horizontal offset in pixels [7:0] pgen_grid_x_offset_x_h 0x060e [7:4] reserved r/w [3:0] 0x0 grid block horizontal offset in pixels [11:8] pgen_grid_y_offset_y_l 0x060f r/w [7:4] 0x0 grid block vertical offset in pixels pgen_grid_y_offset_y_h 0x0610 r/w [3:0]
pattern generator block ade3xxx 62/88 pgen_p0_mode 0x0611 r/w pattern 0 control r/w [7:5] 0x0 number of bars in c0 r/w [4:2] 0x0 number of bars in c1 r/w [1] 0x0 0: pattern continues to progress across block boundaries 1: block boundaries cause the pattern to restart r/w [0] 0x0 0: normal mode 1: c0 = video bypass pgen_p1_mode 0x0612 pattern 1 control r/w [7:5] 0x0 number of bars in c0 r/w [4:2] 0x0 number of bars in c1 r/w [1] 0x0 0: pattern continues to progress across block boundaries 1: block boundaries cause the pattern to restart r/w [0] 0x0 0: normal mode 1: c0 = video bypass pgen_p0_width_x_l 0x0613 r/w [7:0] 0x0 pattern 0 bar width [7:0] pgen_p0_width_x_h 0x0614 [7:4] reserved r/w [3:0] 0x0 pattern 0 bar width [11:8] pgen_p0_width_x_offset_l 0x0615 r/w [7:0] 0x0 pattern 0 horizontal offset [7:0] pgen_p0_width_x_offset_h 0x0616 [7:4] reserved r/w [3:0] 0x0 pattern 0 horizontal offset [11:8] pgen_p0_height_y_l 0x0617 r/w [7:0] 0x0 pattern 0 bar height [7:0] pgen_p0_height_y_h 0x0618 r/w [7:4] 0x0 pattern 0 vertical sequence increment r/w [3:0] 0x0 pattern 0 bar height [11:8] pgen_p0_height_y_offset_l 0x0619 r/w [7:0] 0x0 pattern 0 vertical offset [7:0] pgen_p0_height_y_offset_h 0x061a [7:4] reserved r/w [3:0] 0x0 pattern 0 vertical offset [11:8] pgen_p1_width_x_l 0x061b r/w [7:0] 0x0 pattern 1 bar width [7:0] pgen_p1_width_x_h 0x061c [7:4] reserved r/w [3:0] 0x0 pattern 1 bar width [11:8] pgen_p1_width_x_offset_l 0x061d r/w [7:0] 0x0 pattern 1 horizontal offset [7:0] pgen_p1_width_x_offset_h 0x061e [7:4] reserved r/w [3:0] 0x0 pattern 1 horizontal offset [11:8] pgen_p1_height_y_l 0x061f r/w [7:0] 0x0 pattern 1 bar height [7:0] pgen_p1_height_y_h 0x0620 r/w [7:4] 0x0 pattern 1 vertical sequence increment r/w [3:0] 0x0 pattern 1 bar height [11:8] pgen_p1_height_y_offset_l 0x0621 r/w [7:0] 0x0 pattern 1 vertical offset [7:0] pgen_p1_height_y_offset_h 0x0622 [7:4] reserved r/w [3:0] 0x0 pattern 1 vertical offset [11:8] pgen_p0_color_r_c0 0x0623 r/w [7:0] 0x0 pattern 0 color c0 - red pgen_p0_color_g_c0 0x0624 r/w [7:0] 0x0 pattern 0 color c0 - green pgen_p0_color_b_c0 0x0625 r/w [7:0] 0x0 pattern 0 color c0 - blue pgen_p0_color_r_c1 0x0626 r/w [7:0] 0x0 pattern 0 color c1 - red pgen_p0_color_g_c1 0x0627 r/w [7:0] 0x0 pattern 0 color c1 - green table 21: pgen registers (sheet 2 of 4) register name addr mode bits default description
63/88 ade3xxx pattern generator block pgen_p0_color_b_c1 0x0628 r/w [7:0] 0x0 pattern 0 color c1 - blue pgen_p1_color_r_c0 0x0629 r/w [7:0] 0x0 pattern 1 color c0 - red pgen_p1_color_g_c0 0x062a r/w [7:0] 0x0 pattern 1 color c0 - green pgen_p1_color_b_c0 0x062b r/w [7:0] 0x0 pattern 1 color c0 - blue pgen_p1_color_r_c1 0x062c r/w [7:0] 0x0 pattern 1 color c1 - red pgen_p1_color_g_c1 0x062d r/w [7:0] 0x0 pattern 1 color c1 - green pgen_p1_color_b_c1 0x062e r/w [7:0] 0x0 pattern 1 color c1 - blue pgen_p0_graddelta_r 0x062f r/w [7:0] 0x0 pattern 0 gradient delta on red pgen_p0_graddelta_g 0x0630 r/w [7:0] 0x0 pattern 0 gradient delta on green pgen_p0_graddelta_b 0x0631 r/w [7:0] 0x0 pattern 0 gradient delta on blue pgen_p0_gradstep_x 0x0632 r/w [7:0] 0x0 pattern 0 gradient horizontal step pgen_p0_gradstep_y 0x0633 r/w [7:0] 0x0 pattern 0 gradient vertical step pgen_p1_graddelta_r 0x0634 r/w [7:0] 0x0 pattern 1 gradient delta on red pgen_p1_graddelta_g 0x0635 r/w [7:0] 0x0 pattern 1 gradient delta on green pgen_p1_graddelta_b 0x0636 r/w [7:0] 0x0 pattern 1 gradient delta on blue pgen_p1_gradstep_x 0x0637 r/w [7:0] 0x0 pattern 1 gradient horizontal step pgen_p1_gradstep_y 0x0638 r/w [7:0] 0x0 pattern 1 gradient vertical step pgen_p0_seq_col0_col1 0x0639 [7] reserved r/w [6:4] 0x0 pattern 0 bar 1 color [3] reserved r/w [2:0] 0x0 pattern 0 ba r0 color pgen_p0_seq_col2_col3 0x063a [7] reserved r/w [6:4] 0x0 pattern 0 bar 3 color [3] reserved r/w [2:0] 0x0 pattern 0 bar 2 color pgen_p0_seq_col4_col5 0x063b [7] reserved r/w [6:4] 0x0 pattern 0 bar 5 color [3] reserved r/w [2:0] 0x0 pattern 0 bar 4 color pgen_p0_seq_col6_col7 0x063c [7] reserved r/w [6:4] 0x0 pattern 0 bar 7 color [3] reserved r/w [2:0] 0x0 pattern 0 bar 6 color pgen_p1_seq_col0_col1 0x063d [7] reserved r/w [6:4] 0x0 pattern 1 bar 1 color [3] reserved r/w [2:0] 0x0 pattern 1 bar 0 color pgen_p1_seq_col2_col3 0x063e [7] reserved r/w [6:4] 0x0 pattern 1 bar 3 color [3] reserved r/w [2:0] 0x0 pattern 1 bar 2 color pgen_p1_seq_col4_col5 0x063f [7] reserved r/w [6:4] 0x0 pattern 1 bar 5 color [3] reserved r/w [2:0] 0x0 pattern 1 bar 4 color table 21: pgen registers (sheet 3 of 4) register name addr mode bits default description
srgb block ade3xxx 64/88 2.18 srgb block the srgb block performs two primary functions: 1. parametric gamma correction on multiple windows or full screen for video enhancement in a window and digital contrast/brightness control. the window coordinates are set by tcon registers. 2. 3d color cube warping rgb color space. 2.18.1 parametric gamma correction and digital contrast/brightness control the function is applied to the entire window by programming the window control to full screen. each color channel acts independently. simple digital contrast and brightness are programmable with this hardware function. the desired window coordinates are programmed into the tcon. 2.18.2 color space warp the 8 corners of the color cube are independently controlled in 3d space with smooth interpolation of intermediate colors. registers are 2s complement color deltas. for example, to make white more like red, program srgb_white_r to a small positive value. pgen_p1_seq_col6_col7 0x0640 [7] reserved r/w [6:4] 0x0 pattern 1 bar 7 color [3] reserved r/w [2:0] 0x0 pattern 1 bar 6 color pgen_b_top_bottom 0x0641 r/w [7] 0x0 top border enable r/w [6] 0x0 top border red; 0 = off, 1= on r/w [5] 0x0 top border green; 0 = off, 1= on r/w [4] 0x0 top border blue; 0 = off, 1= on r/w [3] 0x0 bottom border enable r/w [2] 0x0 bottom border red; 0 = off, 1= on r/w [1] 0x0 bottom border green; 0 = off, 1= on r/w [0] 0x0 bottom border blue; 0 = off, 1= on pgen_b_left_right 0x0642 r/w [7] 0x0 left border enable r/w [6] 0x0 left border red; 0 = off, 1= on r/w [5] 0x0 left border green; 0 = off, 1= on r/w [4] 0x0 left border blue; 0 = off, 1= on r/w [3] 0x0 right border enable r/w [2] 0x0 right border red; 0 = off, 1= on r/w [1] 0x0 right border green; 0 = off, 1= on r/w [0] 0x0 right border blue; 0 = off, 1= on pgen_x_total_l 0x0643 r/w [7:0] 0x0 total horizontal size [7:0] pgen_x_total_h 0x0644 [7:4] reserved r/w [3:0] 0x0 total horizontal size [11:8] pgen_y_total_l 0x0645 r/w [7:0] 0x0 total vertical size [7:0] pgen_y_total_h 0x0646 [7:4] reserved r/w [3:0] 0x0 total vertical size [11:8] table 21: pgen registers (sheet 4 of 4) register name addr mode bits default description
65/88 ade3xxx srgb block figure 8: color space warp table 22: srgb registers (sheet 1 of 2) register name addr mode bits default description srgb_ctrl 0x0d00 r/w [7:6] 0x0 reserved r/w [5:4] 0x0 gamma_b control 0x0: disable 0x1: full screen 0x2: windowed 0x3: reserved r/w [3:2] 0x0 gamma_a control 0x0: disable 0x1: full screen 0x2: windowed 0x3: reserved r/w [1:0] 0x0 srgb control 0x0: disabled 0x1: full screen 0x2: windowed 0x3: reserved srgb_black_r 0x0d01 r/w [7:0] 0x0 black point red delta srgb_black_g 0x0d02 r/w [7:0] 0x0 black point green delta srgb_black_b 0x0d03 r/w [7:0] 0x0 black point blue delta srgb_red_r 0x0d04 r/w [7:0] 0x0 red point red delta srgb_red_g 0x0d05 r/w [7:0] 0x0 red point green delta srgb_red_b 0x0d06 r/w [7:0] 0x0 red point blue delta srgb_green_r 0x0d07 r/w [7:0] 0x0 green point red delta srgb_green_g 0x0d08 r/w [7:0] 0x0 green point green delta srgb_green_b 0x0d09 r/w [7:0] 0x0 green point blue delta srgb_blue_r 0x0d0a r/w [7:0] 0x0 blue point red delta srgb_blue_g 0x0d0b r/w [7:0] 0x0 blue point green delta srgb_blue_b 0x0d0c r/w [7:0] 0x0 blue point blue delta srgb_yellow_r 0x0d0d r/w [7:0] 0x0 yellow point red delta srgb_yellow_g 0x0d0e r/w [7:0] 0x0 yellow point green delta srgb_yellow_b 0x0d0f r/w [7:0] 0x0 yellow point blue delta srgb_cyan_r 0x0d10 r/w [7:0] 0x0 cyan point red delta color space warp in out
osd block ade3xxx 66/88 2.19 osd block introduction the integrated on-screen display (osd) controller is a character-based overlay with a high level of features and over 100kbyte of on-board dedicated ram storage. features l 15 row by 30 column character-mapped display l four user-definable windows l 12x18-pixel characters with optional horizontal and vertical doubling on a row-by-row basis l two 16-entry 24-bit rgb user-definable color maps l 192 ram-based monochrome 1bpp characters l 64 ram-based graphics 4bpp characters l text character attributes: foreground/background color, blinking srgb_cyan_g 0x0d11 r/w [7:0] 0x0 cyan point green delta srgb_cyan_b 0x0d12 r/w [7:0] 0x0 cyan point blue delta srgb_magenta_r 0x0d13 r/w [7:0] 0x0 magenta point red delta srgb_magenta_g 0x0d14 r/w [7:0] 0x0 magenta point green delta srgb_magenta_b 0x0d15 r/w [7:0] 0x0 magenta point blue delta srgb_white_r 0x0d16 r/w [7:0] 0x0 white point red delta srgb_white_g 0x0d17 r/w [7:0] 0x0 white point green delta srgb_white_b 0x0d18 r/w [7:0] 0x0 white point blue delta srgb_gamma_a_red_a 0x0d19 r/w [7:0] 0x0 parametric a gamma a red, gamma srgb_gamma_a_red_b 0x0d1a r/w [7:0] 0x0 parametric a gamma b red, contrast srgb_gamma_a_red_c 0x0d1b r/w [7:0] 0x0 parametric a gamma c red, brightness srgb_gamma_a_green_a 0x0d1c r/w [7:0] 0x0 parametric a gamma a green, gamma srgb_gamma_a_green_b 0x0d1d r/w [7:0] 0x0 parametric a gamma b green, contrast srgb_gamma_a_green_c 0x0d1e r/w [7:0] 0x0 parametric a gamma c green, brightness srgb_gamma_a_blue_a 0x0d1f r/w [7:0] 0x0 parametric a gamma a blue, gamma srgb_gamma_a_blue_b 0x0d20 r/w [7:0] 0x0 parametric a gamma b blue, contrast srgb_gamma_a_blue_c 0x0d21 r/w [7:0] 0x0 parametric a gamma c blue, brightness srgb_gamma_b_red_a 0x0d22 r/w [7:0] 0x0 parametric b gamma a red, gamma srgb_gamma_b_red_b 0x0d23 r/w [7:0] 0x0 parametric gamma b red, contrast srgb_gamma_b_red_c 0x0d24 r/w [7:0] 0x0 parametric gamma c red, brightness srgb_gamma_b_green_a 0x0d25 r/w [7:0] 0x0 parametric gamma a green, gamma srgb_gamma_b_green_b 0x0d26 r/w [7:0] 0x0 parametric gamma b green, contrast srgb_gamma_b_green_c 0x0d27 r/w [7:0] 0x0 parametric gamma c green, brightness srgb_gamma_b_blue_a 0x0d28 r/w [7:0] 0x0 parametric gamma a blue, gamma srgb_gamma_b_blue_b 0x0d29 r/w [7:0] 0x0 parametric gamma b blue, contrast srgb_gamma_b_blue_c 0x0d2a r/w [7:0] 0x0 parametric gamma c blue, brightness table 22: srgb registers (sheet 2 of 2) register name addr mode bits default description
67/88 ade3xxx osd block l graphics character attributes: per-pixel color, vertical/horizontal mirroring l row attributes: double width, double height l window attributes: window visibility, position, size, border shadow, color table l global attributes: osd visibility, osd screen position, alpha fade in/fade out, global size doubling, rotation in ninety-degree increments l single-bit enable/disable for information on osd programming, see the osd programming manual. osd access via i2c the osd uses a dedicated memory space accessible through an i2c port. the data stream sent to the osd register starts with two header bytes. these specify the type of transfer and the row/ column position for screen map transfers, the character index for font definition transfers, or the color index for color map transfers. a stream of osd writes to the osd i2c register can fill in a segment of the osd memory space with an internal auto-incrementing index register. the protocol is as follows: 1. issue a start sequence with the r/w bit set to w. 2. write to the osd register. the first byte transferred is the index of the first internal osd register to be written. the next byte contains the data to be written to that register. subsequent bytes are written to successive internal osd registers. 3. continue writing data bytes until the desired range of osd internal registers has been written (the ade3xxx device will issue an ack on each transfer). 4. issue an i2c stop sequence. character display there are two 96-character monochrome fonts and two 32-character four-bit color fon ts, a total of 256 characters. the four bits of color are an index into one of two 16 entry color look-up tables. entries in the color look-up table specify a 24-bit rgb color. all fonts and the color look-up table are ram-based and must be downloaded to the osds internal ram before use. font addressing is as follows: character indexes 0x00-0x1f refer to color font 0, 0x20-0x7f refer to monochrome font 0, 0x80-0x9f refer to color font 1 and 0xa0-0xff refer to monochrome font 1. screen map the osd uses a character map of 15 rows x 30 columns. each character occupies one byte. the value of each byte indicates the character to display. the osd character map is addressed by specifying the row and column as part of the data transfer. attribute map the attribute map is defined as 16 rows by 31 columns. it has an extra row and an extra column compared to the screen map. the values corresponding to printable row/column addresses provide character attributes. each character on the screen has an attribute byte specifying (in the case of monochrome fonts) three bits of background color, four bits of foreground color, and a blink on/off bit. blinking, when enabled, has a period of 100 frames (50 frames on, 50 frames off). column 31 of each row contains row attributes. these include the fourth bit of the background color and two bits controlling double-height and double-width text. row 15 contains global attributes, including vertical and horizontal osd position on the screen, alpha blending, shadow/bordering, osd rotation, color map selection, and normal/double size. alpha blending allows the osd display to be mixed with the incoming video signal for transparency
osd block ade3xxx 68/88 effects. an alpha value of 255 makes the osd opaque, while a value of 0 makes the osd invisible, with a linear ramp of transparency between these two endpoints. separate registers control alpha for foreground and background pixels. a fade-in/fade-out feature ramps the alpha values every six frames, starting from their current value and going up or down the sequence: 0, 16, 32, 64, 128, 192, 224, 240, 255. row 15 also contains definitions for the four display windows. these windows define regions on the screen to which borders and shadows can be applied. (they are not analogous to windows in a gui display, in that they do not represent four independent data displays. there is only one character map. the windows essentially define an area around which a border can be drawn or to which attributes can be assigned.) windows also determine which of the two color tables will be used for the characters inside. windows have a fixed precedence: window 0 has the highest precedence and window 3 the lowest. when windows ove rlap, the precedence determines which borders will be displayed and which color tables will be used in the overlapping area. monochrome and color fonts are affected differently by attribute bytes. monochrome characters are affected by shadows and borders, and have their color specified by the foreground/background attributes. color characters interpret the attribute byte differently than monochrome characters, using it to define blinking and 90-degree rotations rather than blinking, foreground color, and background color. color tables there are two color tables, each containing sixteen entries by three bytes each, giving a 24-bit rgb value for each entry. entry 0 is used for the shadow color for monochrome characters and borders. color-table selection is made on a window-by-window basis. when writing the color table, the row value in the first header byte is interpreted as the color table index, while the column value in the second header byte encoded to select the color table (0 or 1) figure 9: character attribute map character attributes r ow a ttribut es 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 wa wa ga ga wa wa = window attributes ga = global attributes
69/88 ade3xxx osd block and the primary color (red, green, or blue). the data byte following the second header byte is written to the selected (table, index, primary) location. font data font data is sent to the osd through burst transfers. the first header byte selects the transfer type and provides three bits of the character index, while the second header byte selects transfer type c and gives the remaining five bits of offset. the data bytes for the character follow, given from top to bottom and left to right in the character cell. a monochrome character is 27 bytes long, with two scan-lines occupying three bytes. a color character is four times as long as a monochrome character (108 bytes), with each byte containing two four-bit pixels. both color and monochrome fonts are 12 pixels wide and 18 high. transfer formats the transfer format consists of two header bytes and a variable number of data bytes. the header bytes determine the type of transfer (character, attribute, monochrome font, color font, or color table). addressing is by row and column in the case of character or attribute transfers, and by character index in the case of font transfers. when writing to the color table, the column field determines the color table and r/g/b selection. table 23: osd access header definition header byte bits description first [7:4] type of data transfer. valid values are: 0x8: screen map 0x9: color lut 0xa: attribute map 0xc: font data all others: reserved [3:0] for screen map or attribute map access, this is the row index. for color lut access, this is the color index. for font data access, bits [2:0] are the msbs of the character index. second [7:6] type of data burst: 0x0: a/b modes: only one data byte follows this header byte. 0x1: c mode: all bytes following this header byte are data bytes until the serial interface indicates an end-of-transmission. the osd internally auto-increments after each byte. in screen and attribute map access modes the column number is incremented after each byte, wrapping to the beginning of the next row once column 29 is passed and wrapping to row 0 if row 14 is passed. either mode may be used for display and character attribute modes, except for the off-screen attributes in column 15 and row 30, which must use mode a/b. font definition mode must use mode c. [5] must be set to zero [4:0] in screen and attribute map access modes, this is the column number. in font data access mode, this gives the 5 lsbs of the character index. in color lut access mode, it selects the table number and color to be written: 0x0: lut 0, red 0x1: lut 0, green 0x2: lut 0, blue 0x3: lut 1, red 0x4: lut 1, green 0x5: lut 1, blue 0x6 - 0x7: reserved
osd block ade3xxx 70/88 table 24: osd attribute map definition (sheet 1 of 2) row column bits description 15 12 [7:0] vertical osd position / 4 15 13 [7:0] horizontal osd position / 5 15 15 [7] 0: osd off 1: osd on [6:5] 0x0: plain characters 0x1: border characters 0x2: shadow characters 0x3: reserved [4:3] reserved [2] 0: normal 1: flip osd [1] 0: fade off 1: fade on [0] 0: normal size 1: double size 15 19 [7:0] foreground alpha blending 15 20 [7:0] background alpha blending 15 0 [7:4] window 0 row start [3:0] window 0 row end 15 3 [7:4] window 1 row start [3:0] window 1 row end 15 6 [7:4] window 2 row start [3:0] window 2 row end 15 9 [7:4] window 3 row start [3:0] window 3 row end 15 1 [7:3] window 0 column start [2] window 0 visibility 0: off 1: on [1] reserved [0] window 0 shadow enable 15 4 [7:3] window 1 column start [2] window 1 visibility 0: off 1: on [1] reserved [0] window 1 shadow enable 15 7 [7:3] window 2 column start [2] window 2 visibility 0: off 1: on [1] reserved [0] window 2 shadow enable
71/88 ade3xxx osd block 15 10 [7:3] window 3 column start [2] window 3 visibility 0: off 1: on [1] reserved [0] window 3 shadow enable 15 2 [7:3] window 0 column end [2:0] reserved 15 5 [7:3] window 1 column end [2:0] reserved 15 8 [7:3] window 2 column end [2:0] reserved 15 11 [7:3] window 3 column end [2:0] reserved 15 16 [7:6] window 3 shadow width [5:4] window 2 shadow width [3:2] window 1 shadow width [1:0] window 0 shadow width 15 17 [7:6] window 3 shadow height [5:4] window 2 shadow height [3:2] window 1 shadow height [1:0] window 0 shadow height 15 21 [7:4] reserved [3] window 3 color lut select [2] window 2 color lut select [1] window 1 color lut select [0] window 0 color lut select 0 to 14 30 [7:3] reserved [2] msb of background color for the row [1] double high enable for the row [0] double wide enable for the row 0 to 14 0 to 29 [7:5] 3 lsbs of background color for 1bpp chars no function for 4bpp color chars [4] blink enable [3:0] foreground color for 1bpp chars for 4bpp color chars [3:2]: reserved [1]: flip vertical [0]: flip horizontal table 24: osd attribute map definition (sheet 2 of 2) row column bits description
flicker block ade3xxx 72/88 2.20 flicker block the flicker block computes correlations of the image data with potential inversion patterns of the lcd which in turn allows the microcontroller to modify the polarity signal to cancel large area flicker. this function is only useful in smartpanel applications. the incoming image is scored against 8 vertical walsh functions. all patterns are considered to be vertically, where horizontally the pixels are assumed to be alternating its rgb components. the scores (0 to 7) are 32-bit unsigned quantities that reflect the correlation of the programmed window area with the 8 walsh functions. the horizontal inversion of the lcd drivers must be programmed into flicker_ctrl0[2:0]. the most common setting is +-+ or -+- (rgb). a calculation is completed after the number of frames programmed into the frame_cnt_max reg (0xca03). with each frame, the calculation is performed on only a vertical strip. the width of that strip (in pixels) is determined by the value programmed in the hblock_size reg (0xca02) with the following relation: strip width = 2 ^ (3 + hblock_size). the free_run/freeze_scores bit (flicker_ctrl0[4]) enables the final calculation to be captured easily by the microntroller. the internal flicker calculation continues to run -- only the update of the i2c registers is blocked when this bit is set to prevent corrupution during readout. table 25: osd register register name addr mode bits default description osd_port 0c02 r/w [7:0] 0 osd access port table 26: flicker registers (sheet 1 of 3) register name addr mode bits default description flk_ctrl 0x0ca1 r/w [7:6] 0x0 reserved w [5] 0x1 0: straight line uniform function 1: straight line hill function (normal) r/w [4] 0x0 0: free run 1: freeze scores set to a 1 when the microcontroller is reading multibyte scores to prevent update corruption. r/w [2:0] 0x25 horizontal subpixel polarity inversion pattern of lcd (even/odd pixels) 0x0: -r-g-b / +r+g+b 0x1: -r-g+b / +r+g-b 0x2: -r+g-b / +r-g+b (normal) 0x3: -r+g+b / +r-g-b 0x4: +r-g-b / -r+g+b 0x5: +r-g+b / -r+g-b (normal) 0x6: +r+g-b / -r-g+b 0x7: +r+g+b / -r-g-b flk_hblock_size 0x0ca2 r/w [7:4] reserved [3:0] 0x0 width in pixels of the per frame scored area = 2 ^ (3+ hblock_size)
73/88 ade3xxx flicker block flk_frame_cnt_max 0x0ca3 r/w [7:0] 0x8 number of frames to complete one measurement total number of pixels in a line is: frame_cnt_max x (2 ^ (3 + hblock_size) ) example: hblock_size = 4; frame_cnt_max = 8; in each frame only one portion of the image is being scored. the width of that portion is 2 ^ (3 + hblock_size) = 128 pixels and the height is the full height of the image. thus the total scored area after 8 frames is 128 x 8 = 1024 pixels wide. flk_meas0_0 0x0cb1 r/w [7:0] 0x0 score for pattern 0 flk_meas0_1 0x0cb2 r/w [7:0] flk_meas0_2 0x0cb3 r/w [7:0] flk_meas0_3 0x0cb4 r/w [7:0] flk_meas1_0 0x0cb5 r/w [7:0] 0x0 score for pattern 1 flk_meas1_1 0x0cb6 r/w [7:0] flk_meas1_2 0x0cb7 r/w [7:0] flk_meas1_3 0x0cb8 r/w [7:0] flk_meas2_0 0x0cb9 r/w [7:0] 0x0 score for pattern 2 flk_meas2_1 0x0cba r/w [7:0] flk_meas2_2 0x0cbb r/w [7:0] flk_meas2_3 0x0cbc r/w [7:0] flk_meas3_0 0x0cbd r/w [7:0] 0x0 score for pattern 3 flk_meas3_1 0x0cbe r/w [7:0] flk_meas3_2 0x0cbf r/w [7:0] flk_meas3_3 0x0cc0 r/w [7:0] flk_meas4_0 0x0cc1 r/w [7:0] 0x0 score for pattern 4 flk_meas4_1 0x0cc2 r/w [7:0] flk_meas4_2 0x0cc3 r/w [7:0] flk_meas4_3 0x0cc4 r/w [7:0] flk_meas5_0 0x0cc5 r/w [7:0] 0x0 score for pattern 5 flk_meas5_1 0x0cc6 r/w [7:0] flk_meas5_2 0x0cc7 r/w [7:0] flk_meas5_3 0x0cc8 r/w [7:0] flk_meas6_1 0x0cc9 r/w [7:0] 0x0 score for pattern 6 flk_meas6_2 0x0cca r/w [7:0] flk_meas6_3 0x0ccb r/w [7:0] flk_meas6_4 0x0ccc r/w [7:0] table 26: flicker registers (sheet 2 of 3) register name addr mode bits default description
gamma block ade3xxx 74/88 2.21 gamma block the gamma block performs an 8 bit to 10 bit lookup table on the 3 x 8 bits (r, g, b) color data coming from scaler. the rams are individually programmable (read and write) using i2c access. the memory map is as follows: i2c address 0x1000 - 0x11ff: red ram i2c address 0x1200 - 0x13ff: green ram i2c address 0x1400 - 0x15ff: blue ram even addresses are the 8-bit lsbs of the 10-bit gamma value. odd addresses are the 2 msbs. 2.22 apc block apc (formerly known as arithmos perfect color) dithers an input 10-bit video stream down to 4-8 output bits. the dithering is done in space and time in such a way that the eye does not perceive objectionable artifacts such as: l fixed dither patterns, l contours, l flickering pixels l phase correlated flickering, which creates wave patterns known as "swimming". flk_meas7_0 0x0ccd r/w [7:0] 0x0 score for pattern 7 flk_meas7_1 0x0cce r/w [7:0] flk_meas7_2 0x0ccf r/w [7:0] flk_meas7_3 0x0cd0 r/w [7:0] table 27: gamma registers register name addr mode bits default description gamma_ctrl 0x0c10 r/w [7:4] 0x0 reserved [3] 0x0 0: normal 1: disable ram access [2] 0x0 0: normal 1: test mode [1:0] 0x0 gamma mode select 0x0: 10b linear bypass 0x1: 8b->10b gamma table (normal) 0x2: 8b linear bypass (no interpolation) 0x3: 8b->10b gamma table (normal) table 26: flicker registers (sheet 3 of 3) register name addr mode bits default description
75/88 ade3xxx output mux block 2.23 output mux block table 28: apc registers register name addr mode bits default description apc_apc0 0x0c20 [7] reserved r/w [6:5] 0x0 frame modulation period - 1 r/w [4:1] 0x0 0x0 - 0x3: 8b out 0x4: 4-bit output 0x5: 5-bit output 0x6: 6-bit output 0x7: 7-bit output 0x8: 8-bit output r/w [0] 0x0 0: normal 1: disable apc -- truncate lsbs apc_apc1 0x0c21 [7:2] reserved r/w [1] 0x0 offset the phase lut r/w [0] 0x0 offset the dither lut table 29: output mux registers (sheet 1 of 3) register name addr mode bits default description omux_ctrl_0 0x0c30 r/w [7] 0x0 in 2 ppc, 0: data invert for a+b comb. 1: data invert a/b separate r/w [6:4] 0x0 0x0 - 0x4: right shift per 8b r/g/b 0x5 - 0x7: reserved r/w [3] 0x0 0: normal 1: flip msbs to lsbs r/w [2] 0x0 0: normal 1: swap r and b data r/w [1] 0x0 0: in 1 ppc, a channel active 0: in 2 ppc, left on a, right on b 1: in 1 ppc, b channel active 1: 2ppc, left on b, right on a r/w [0] 0x0 0: single wide, one pix/clk (ppc) 1: double wide, two pix/clk omux_ctrl_1 0x0c31 r/w [7] 0x0 vsync output polarity r/w [6] 0x0 hsync output polarity r/w [5] 0x0 data enable output polarity r/w [4] 0x0 clock output invert r/w [3] 0x0 data invert output polarity r/w [2] 0x0 data invert enable r/w [1] 0x0 0: tcon outputs set to zero 1: tcon outputs active r/w [0] 0x0 0: all data outputs set to zero 1: output enabled
output mux block ade3xxx 76/88 omux_ctrl_2 0x0c32 r/w [7] 0x0 seperate tcon driven invert enable r/w [6] 0x0 tcon driven invert pin enable r/w [5] 0x0 rsds enable r/w [4] 0x0 per pin delay enable r/w [3] 0x0 resync on vsync falling edge r/w [2] 0x0 resync on vsync rising edge r/w [1] 0x0 resync on hsync falling edge r/w [0] 0x0 resync on hsync rising edge omux_dly_ba0 0x0c50 r/w [7:4] 0x0 delay for oba1 r/w [3:0] 0x0 delay for oba0 omux_ dly_ba2 0x0c4f r/w [7:4] 0x0 delay for oba3 r/w [3:0] 0x0 delay for oba2 omux_ dly_ba4 0x0c4e r/w [7:4] 0x0 delay for oba5 r/w [3:0] 0x0 delay for oba4 omux_ dly_ba6 0x0c4d r/w [7:4] 0x0 delay for oba7 r/w [3:0] 0x0 delay for oba6 omux_ dly_ga0 0x0c4c r/w [7:4] 0x0 delay for oga1 r/w [3:0] 0x0 delay for oga0 omux_ dly_ga2 0x0c4b r/w [7:4] 0x0 delay for oga3 r/w [3:0] 0x0 delay for oga2 omux_ dly_ga4 0x0c4a r/w [7:4] 0x0 delay for oga5 r/w [3:0] 0x0 delay for oga4 omux_ dly_ga6 0x0c49 r/w [7:4] 0x0 delay for oga7 r/w [3:0] 0x0 delay for oga6 omux_ dly_ra0 0x0c48 r/w [7:4] 0x0 delay for ora1 r/w [3:0] 0x0 delay for ora0 omux_ dly_ra2 0x0c47 r/w [7:4] 0x0 delay for ora3 r/w [3:0] 0x0 delay for ora2 omux_ dly_ra4 0x0c46 r/w [7:4] 0x0 delay for ora5 r/w [3:0] 0x0 delay for ora4 omux_ dly_ra6 0x0c45 r/w [7:4] 0x0 delay for ora7 r/w [3:0] 0x0 delay for ora6 omux_ dly_bb0 0x0c44 r/w [7:4] 0x0 delay for obb1 r/w [3:0] 0x0 delay for obb0 omux_ dly_bb2 0x0c43 r/w [7:4] 0x0 delay for obb3 r/w [3:0] 0x0 delay for obb2 omux_ dly_bb4 0x0c42 r/w [7:4] 0x0 delay for obb5 r/w [3:0] 0x0 delay for obb4 omux_ dly_bb6 0x0c41 r/w [7:4] 0x0 delay for obb7 r/w [3:0] 0x0 delay for obb6 omux_ dly_gb0 0x0c40 r/w [7:4] 0x0 delay for ogb1 r/w [3:0] 0x0 delay for ogb0 omux_ dly_gb2 0x0c3f r/w [7:4] 0x0 delay for ogb3 r/w [3:0] 0x0 delay for ogb2 table 29: output mux registers (sheet 2 of 3) register name addr mode bits default description
77/88 ade3xxx pulse width modulation (pwm) block 2.24 pulse width modulation (pwm) block the pwm b block generates two signals to control backlight inverter switching power components directly. it is derived from xclk and powered up independently of the dotclk and inclk domains. frequency, duty cycle, polarity and overlap/non-ove rlap are programmable. the output frequency can free-run or lock to output vsync. omux_ dly_gb4 0x0c3e r/w [7:4] 0x0 delay for ogb5 r/w [3:0] 0x0 delay for ogb4 omux_ dly_gb6 0x0c3d r/w [7:4] 0x0 delay for ogb7 r/w [3:0] 0x0 delay for ogb6 omux_ dly_rb0 0x0c3c r/w [7:4] 0x0 delay for orb1 r/w [3:0] 0x0 delay for orb0 omux_ dly_rb2 0x0c3b r/w [7:4] 0x0 delay for orb3 r/w [3:0] 0x0 delay for orb2 omux_ dly_r_b4 0x0c3a r/w [7:4] 0x0 delay for orb5 r/w [3:0] 0x0 delay for orb4 omux_ dly_r_b6 0x0c39 r/w [7:4] 0x0 delay for orb7 r/w [3:0] 0x0 delay for orb6 omux_ dly_tcon_0 0x0c38 r/w [7:4] 0x0 delay for tcon1 r/w [3:0] 0x0 delay for tcon0 omux_ dly_tcon_2 0x0c37 r/w [7:4] 0x0 delay for tcon3 r/w [3:0] 0x0 delay for tcon2 omux_ dly_tcon_4 0x0c36 r/w [7:4] 0x0 delay for tcon5 r/w [3:0] 0x0 delay for tcon4 omux_ dly_tcon_6 0x0c35 r/w [7:4] 0x0 delay for tcon7 r/w [3:0] 0x0 delay for tcon6 omux_ dly_vs_enab 0x0c34 r/w [7:4] 0x0 delay for vsync r/w [3:0] 0x0 delay for enab omux_ dly_clk_hs 0x0c33 r/w [7:4] 0x0 delay for clk r/w [3:0] 0x0 delay for hsync omux_ctrl_3 0x0c51 r/w [7:3] reserved r/w [2] 0x0 pwm mux mode r/w [1] 0x0 pwm enable r/w [0] 0x0 tcon data invert enable, with computed data invert pin. omux_refcount 0x0c52 [7:6] reserved r [5:0] 0x0 returns a value that indicates the ade gate speed -- a function of temp and voltage higher = faster logic table 29: output mux registers (sheet 3 of 3) register name addr mode bits default description
pulse width modulation (pwm) block ade3xxx 78/88 table 30: pwm registers register name addr mode bits default description pwm_ctrl0 0x01a0 r [7] 0x0 pwm status 0: unlocked 1: locked r/w [6] 0x0 0: lock to cycles_per_frame from the free run state machine 1: lock to cycles_per_frame register setting r/w [5] 0x0 pwm_a polarity 0: active low 1: active high r/w [4] 0x0 pwm_b polarity 0: active low 1: active high r/w [3] 0x0 0: normal operation 1: force pwm outputs to polarity settings r/w [2] 0x0 0: change period or duty cycle at the end of the current cycle 1: smooth change, period or duty cycle increment/decrement every pwm_step_delay cycle r/w [1] 0x0 0: free run 1: lock to out_vsync r/w [0] 0x0 0: disable pwm output 1: enable pwm output pwm_ctrl1 0x01a1 r/w [7:4] 0x0 lock 2 nd order gain (power of 2) 0x0 = max 0x3 = typical 0xf = min r/w [3:0] 0x0 lock gain (power of 2) 0x0 = max 0x6 = typical 0xf = min pwm_period_l 0x01a2 r/w [7:0] 0x0 period-2 in free-running mode, in xclks pwm_period_h 0x01a3 r/w [7:0] pwm_duty_l 0x01a4 r/w [7:0] 0x0 duty cycle of pwm in xclks pwm_duty_h 0x01a5 r/w [7:0] pwm_overlap_l 0x01a6 r/w [7:0] 0x0 non-overlap of pwms in xclks pwm_overlap_h 0x01a7 r/w [7:0] pwm_step_delay 0x01a8 r/w [7:0] 0x0 in smooth change mode, the number of cycles skipped before the period/duty registers are incremented/decremented pwm_cycles_per_frame_l 0x01a9 r/w [7:0] 0x0 the number of cycles per frame in frame lock mode when not using the internally generated cycles per frame from a previous freerun mode pwm_cycles_per_frame_h 0x01aa r/w [7:0]
79/88 ade3xxx dft block 2.25 dft block table 31: dft registers (sheet 1 of 2) register name addr mode bits default description dft_test_mode 0x0f00 [7:4] reserved r/w [3] 0x0 trigger video bus mfsr r/w [2] 0x0 enable output pin mfsr r/w [1] 0x0 clear output pin mfsr r/w [0] 0x0 output pin test override dft_mux_out_mode 0x0f01 [7:6] reserved r/w [5:0] 0x0 mux selector for output porta/b and syncs dft_flop_out_mode 0x0f02 [7:6] reserved r/w [5:0] 0x0 mux selector for synchronous digital debug bus dft_clk_0ut_mode 0x0f03 r/w [7:6] 0x0 divide-by selector for clocks to oclk pin fout = selected clock / (2 ^ value) r/w [5:0] 0x0 mux selector for clocks to oclk pin dft_clk_1_mode 0x0f04 r/w [7:6] 0x0 divide-by selector for clocks to clkout pin fout = selected clock / (2 ^ value) dft_clk_2_mode 0x0f05 r/w [5:0] 0x0 mux selector for clocks to clkoutpin dft_out_disab_0 0x0f06 r/w [7:0] 0x0 disable porta red output in test mode dft_out_disab_1 0x0f07 r/w [7:0] 0x0 disable porta green output in test mode dft_out_disab_2 0x0f08 r/w [7:0] 0x0 disable porta blue output in test mode dft_out_disab_3 0x0f09 r/w [7:0] 0x0 disable portb red output in test mode dft_out_disab_4 0x0f0a r/w [7:0] 0x0 disable portb green output in test mode dft_out_disab_5 0x0f0b r/w [7:0] 0x0 disable portb blue output in test mode dft_out_disab_6 0x0f0c r/w [7:3] 0x0 disable tcon bits [4:0] in test mode r/w [2] 0x0 disable vert sync output in test mode r/w [1] 0x0 disable data enab output in test mode r/w [0] 0x0 disable horz sync output in test mode dft_out_disab_7 0x0f0d [7:5] reserved r/w [4] 0x0 disable clkout output in test mode r/w [3] 0x0 disable oclk output in test mode r/w [2:0] 0x0 disable tcon bits [7:5] in test mode dft_stim_ctrl 0x0f0e [7:6] reserved r/w [0] 0x0 internal stimulus bus enable dft_stim_en_0 0x0f0f r/w [7] 0x0 scl test stimulus enable r/w [6] hdcp test stimulus enable r/w [5] dvi test mode enable r/w [4] dvi blue test stimulus enable r/w [3] dvi green test stimulus enable r/w [2] 0x0 dvi red test stimulus enable r/w [1] 0x0 adc test stimulus enable r/w [0] 0x0 yuv test stimulus enable
i2c ram addresses ade3xxx 80/88 2.26 i2c ram addresses dft_stim_en_1 0x0f10 [7:6] reserved r/w [5] 0x0 tcon test bypass r/w [4] 0x0 omux test stimulus enable r/w [3] 0x0 apc test stimulus enable r/w [2] 0x0 osd test stimulus enable r/w [1] 0x0 scl bypass r/w [0] 0x0 pgen test stimulus enable dft_bist_status 0x0f11 [7:6] reserved r [5] gamma ram bist end r [4] osd cs ram bist end r [3] osd drb ram bist r [2] osd mb ram bist end r [1] scl coeff. ram bist end r [0] scl line buffer ram bist end dft_bist_result_0 0x0f12 [7:6] reserved r [5] scl coeff ram 2 bist fail r [4] scl coeff ram 1 bist fail r [3] scl line buffer 4 bist fail r [2] scl line buffer 3 bist fail r [1] scl line buffer 2 bist fail r [0] scl line buffer 1 bist fail dft_bist_result_1 0x0f13 [7] reserved r [6] gamma blue ram bist fail r [5] gamma green ram bist fail r [4] gamma red ram bist fail r [3] osd cs ram1 bist fail r [2] osd cs ram 2 bist fail r [1] osd drb ram bist fail r [0] osd mb ram bist fail dft_mfsr_done 0x0f14 [7:1] reserved r [0] done signal dft_mfsr_sig_0 0x0f15 r [7:0] 0x0 video bus mfsr dft_mfsr_sig_1 0x0f16 r [7:0] dft_mfsr_sig_2 0x0f17 r [7:0] dft_mfsr_sig_3 0x0f18 r [7:0] table 32: i2c ram addresses name start addr. end addr. description gam_red 0x1000 0x11ff gamma lut, red, lsb0,msb0,lsb1,... (256x10) gam_green 0x1200 0x13ff gamma lut, green, (256x10) gam_blue 0x1400 0x15ff gamma lut, blue, (256x10) table 31: dft registers (sheet 2 of 2) register name addr mode bits default description
81/88 ade3xxx i2c ram addresses osd_mb 0x1700 0x175f osd color luts (32x24) osd_cs 0x3000 0x5f3f osd character map (1344x36x2 copies) osd_drb 0x6000 0x647f osd screen map (1152x8) scl_coeff 0x9000 0x98ff scaler coefficient ram (256x36x2 copies) scl_line1 0x9900 0xa7ff scaler line buffer 1 (1280x24) scl_line2 0xa800 0xb6ff scaler line buffer 2 (1280x24) scl_line3 0xb700 0xc5ff scaler line buffer 3 (1280x24) scl_line4 0xc600 0xd4ff scaler line buffer 4 (1280x24) table 32: i2c ram addresses name start addr. end addr. description
absolute maximum ratings ade3xxx 82/88 3 electrical specifications 3.1 absolute maximum ratings 3.2 power consumption matrices * measured at nominal voltage supplies ** measured at +10% voltage supplies symbol parameter min typ max unit avdd18 dvdd18 xvdd18 lvdd18 supply voltage 1.95 v avdd33 dvdd33 supply voltage 3.6 v vin max voltage on 5 volt tolerant input pins 6.1 v t stg storage temperature -40 +150 c table 33: ade3100 symbol parameter min typ* max** unit supply current (analog input, xga@75hz, 78.75mhz) i avdd18 1.8v analog supply (i avdd18 ) 188 197 ma i dvdd18 1.8v digital supply (i dvdd18 ) 213 240 ma i avdd33 3.3v analog supply ( iavdd33 ) 109 113 ma i dvdd33 3.3v digital supply (i dvdd33 ) 6469ma supply current (dvi input, xga@75hz, 78.75mhz) i avdd18 1.8v analog supply (i avdd18 ) 5767ma i dvdd18 1.8v digital supply (i dvdd18 ) 222 250 ma i avdd33 3.3v analog supply (i avdd33 ) 109 115 ma i dvdd33 3.3v digital supply (i dvdd33 ) 5967ma supply current (stand by mode) i avdd18 1.8v analog supply (i avdd18 )3.43.9ma i dvdd18 1.8v digital supply (i dvdd18 )3.95.4ma i avdd33 3.3v analog supply (i avdd33 )0.53.9ma i dvdd33 3.3v digital supply (i dvdd33 )2.53.0ma p totana total power consumption (analog input, xga@75hz, 78.75mhz) 1.55 1.85 w p totdvi total power consumption (dvi input, xga@75hz, 78.75mhz) 1.4 1.73 w p standby total power consumption (stand by mode) 23.2 39.4 mw
83/88 ade3xxx nominal operating conditions * measured at nominal voltage supplies ** measured at +10% voltage supplies 3.3 nominal operating conditions table 34: ade3300 symbol parameter min typ* max** unit supply current (analog input, xga@75hz, 135mhz) i avdd18 1.8v analog supply (i avdd18 ) 193 199 ma i dvdd18 1.8v digital supply (i dvdd18 ) 346 380 ma i avdd33 3.3v analog supply ( iavdd33 ) 109 113 ma i dvdd33 3.3v digital supply (i dvdd33 ) 6782ma supply current (dvi input, xga@75hz, 135mhz) i avdd18 1.8v analog supply (i avdd18 ) 5868ma i dvdd18 1.8v digital supply (i dvdd18 ) 371 415 ma i avdd33 3.3v analog supply (i avdd33 ) 114 120 ma i dvdd33 3.3v digital supply (i dvdd33 ) 7794ma supply current (stand by mode) i avdd18 1.8v analog supply (i avdd18 )3.4ma i dvdd18 1.8v digital supply (i dvdd18 )3.9ma i avdd33 3.3v analog supply (i avdd33 )3.9ma i dvdd33 3.3v digital supply (i dvdd33 )3.9ma p totana total power consumption (analog input, xga@75hz, 135mhz) 1.55 1.85 w p totdvi total power consumption (dvi input, xga@75hz, 135mhz) 1.4 1.73 w p standby total power consumption (stand by mode) 38.9 mw symbol parameter min typ max unit avdd18 dvdd18 xvdd18 lvdd 18 supply voltage 1.71 1.8 1.89 v avdd33 dvdd33 supply voltage 3.135 3.3 3.465 v f xtal crystal frequency 27 mhz t oper ambient operating temperature 0 +70 c
preliminary thermal data ade3xxx 84/88 3.4 preliminary thermal data 3.5 preliminary dc specifications test conditions: dvdd33 = avdd33 = 3.3v, dvdd18 = avdd18 = xvdd18 = lvdd18 = 1.8v, and t amb = 25c 3.5.1 lvttl 5 volt tolerant inputs with hysteresis yuv[0:7], yuvclk, hsync, vsync, csync, tcon_in, scl, resetn 3.5.2 lvttl 5 volt tolerant inputs xclk_en 3.5.3 lvttl 5 volt tolerant i/o with hysteresis sda 3.5.4 lvttl outputs oba[0:7], oga[0:7], ora[0:7], obb[0:7], ogb[0:7], orb[0:7], ohs, ovs, ode, oclk symbol parameter min typ max unit r thja junction-to-ambient thermal resistance 25 c/w symbol parameter condition min typ max unit v ih high level input voltage 2.0 v v il low level input voltage 0.8 v v hyst schmitt trigger hysteresis 0.4 v symbol parameter condition min typ max unit v ih high level input voltage 2.0 v v il low level input voltage 0.8 v symbol parameter condition min typ max unit v ih high level input voltage 2.0 v v il low level input voltage 0.8 v v hyst schmitt trigger hysteresis 0.4 v symbol parameter condition min typ max unit v ih high level input voltage 2.0 v v il low level input voltage 0.8 v i ih high level input current vin = vdd -10 a
85/88 ade3xxx preliminary ac specifications 3.6 preliminary ac specifications i il low level input current vin = 0v 10 a symbol parameter condition min typ max unit fdvi dvi input pixel frequency 20 140 mhz vdvi_diff dvi differential input voltage 150 1200 mv vdvi_icm dvi input common mode voltage avdd33 - 0.3 avdd33 - 0.037 v vdvi_vin dvi input voltage when tx disabled or disconnected avdd33 - 0.01 avdd33 + 0.01 v idvi_leak dvi input leackage current rx powered down 10 a rdvi_term dvi input termination resistance rext = 470 ohms 45 50 55 ohm vrsds_diff rsds differential output voltage rsds mode 100 200 400 mv vrsrs_cm rsds common mode output voltage 680 ohm + 50 ohm external termination to 1.3v 1.1 1.3 1.5 v trise, tfall rsds transition time to 90% cl = 30pf 3 ns inl adc integral nonlinearity (9b) 1.5 lsb dnl adc differential nonlinearity (9b) no missing codes 1.5 lsb vadc_in adc input voltage range 0.5 1 vp-p enob adc effective number of bits 135msps input = 65mhz sine at 95% fs 7.5 bits radc_in adc input resistance 200 kohms cadc_in adc input capacitance 8 pf fadc adc sample frequency 20 140 mhz adc gain step adc gain step size 0.05 db adc offset step adc offset step size 4 mv cadc_ext adc external ac coupling cap 0.1 uf symbol parameter condition min typ max unit
preliminary ac specifications ade3xxx 86/88 4 package mechanical data note: exact shape of each corner is optional dimensions (mm) dimensions (inches) min. typ. max. min. typ. max. a 4.10 0.161 a1 0.25 0.30 0.40 0.010 a2 3.20 3.40 3.60 0.126 0.134 0.142 b 0.17 0.27 0.007 0.011 c 0.09 0.20 0.003 0.008 d 30.60 1.205 d1 28.00 1.102 d3 25.50 1.004 e 0.50 0.020 e 30.60 1.205 e1 28.00 1.102 e3 25.50 1.004 l 0.45 0.60 0.75 0.018 0.024 0.029 l1 1.30 0.051 k 0 (min.), 3.5(typ.), 7(max.) a a2 a1 b c 52 53 104 105 156 157 208 e3 d3 e1 e d1 d e 1 k b l l1 gage plane 0.25 mm .010 in. pin 1 identification seating plane 0.076 mm .003 inch exact shape of each corner is optional
87/88 ade3xxx preliminary ac specifications 5 revision history table 35: summary of modifications version date description of modification 0.1 22 oct. 2002 first issue 1.0 25 nov 2002 update of registers smeas_v_ctrl , smux_ctrl0 and flk_ctrl . 1.1 05 feb 2003 changed "projection display engine" to "lcd display engine" on page 1. changed header name ade3500x/3600x to ade3xxx on page 2. 1.2 18 apr 2003 deletion of yuv port information. 1.3 10 july 2003 inclusion of section 3.2: power consumption matrices on page 82 . 1.4 17 july 2003 re-insertion of yuv port information.
88/88 ade3xxx information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics - all rights reserved purchase of i 2 c components by stmicroelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states. www.st.com

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